[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings

[Jérémy Compostella (Code Review)]

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86532?usp=email )

Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
......................................................................

soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings

This commit centralizes the configuration of the Firmware Support
Package for Memory (FSP-M) early Sign-of-Life (SoL) into a common
function to reduce code duplication and enhance maintainability.

This refactoring aims to improve code readability and reduce potential
bugs by having a single source of truth for SoL configuration across
different platforms.

Since the Updateable Product Data (UPD) definitions for VGAInitControl
differ between Meteor Lake and Panther Lake, and because the list of
currently supported uses also varies between the two, the
decision-making process is still being conducted within the SoC (System
on Chip)-specific codebase.

TEST=FSP-M early SoL functionality was verified on Pantherlake platform.

Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5
Signed-off-by: Jeremy Compostella 
---
M src/soc/intel/common/Makefile.mk
A src/soc/intel/common/fsp_esol.c
A src/soc/intel/common/fsp_esol.h
M src/soc/intel/meteorlake/romstage/fsp_params.c
M src/soc/intel/pantherlake/romstage/fsp_params.c
5 files changed, 45 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/86532/1

diff --git a/src/soc/intel/common/Makefile.mk b/src/soc/intel/common/Makefile.mk
index b273ed7..241ba4f 100644
--- a/src/soc/intel/common/Makefile.mk
+++ b/src/soc/intel/common/Makefile.mk
@@ -11,6 +11,7 @@

romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 romstage-$(CONFIG_MMA) += mma.c
+romstage-$(CONFIG_FSP_UGOP_EARLY_SIGN_OF_LIFE) += fsp_esol.c
 romstage-y += smbios.c

postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/common/fsp_esol.c b/src/soc/intel/common/fsp_esol.c
new file mode 100644
index 0000000..b5338b9
--- /dev/null
+++ b/src/soc/intel/common/fsp_esol.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootmode.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/intel/common/fsp_esol.h>
+#include <ux_locales.h>
+
+void fsp_set_esol_params(uint32_t vga_init_control, FSP_M_CONFIG *m_cfg)
+{
+	void *vbt;
+	size_t vbt_size;
+
+	vbt = cbfs_map("vbt.bin", &vbt_size);
+	if (!vbt) {
+		printk(BIOS_ERR, "Could not load vbt.bin\n");
+		return;
+	}
+
+	printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n");
+
+	m_cfg->VgaInitControl = vga_init_control;
+	m_cfg->VbtPtr = (efi_uintn_t)vbt;
+	m_cfg->VbtSize = vbt_size;
+	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
+	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
+
+}
diff --git a/src/soc/intel/common/fsp_esol.h b/src/soc/intel/common/fsp_esol.h
new file mode 100644
index 0000000..992142b
--- /dev/null
+++ b/src/soc/intel/common/fsp_esol.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _INTEL_COMMON_FSP_ESOL_H_
+#define _INTEL_COMMON_FSP_ESOL_H_
+
+void fsp_set_esol_params(uint32_t vga_init_control, FSP_M_CONFIG *m_cfg);
+
+#endif	/* _INTEL_COMMON_FSP_ESOL_H_ */
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index dd9d2b5..bcd384f 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <assert.h>
-#include <bootmode.h>
 #include <console/console.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/intel/cpu_ids.h>
@@ -19,6 +18,7 @@
 #include <option.h>
 #include <soc/cpu.h>
 #include <soc/gpio_soc_defs.h>
+#include <soc/intel/common/fsp_esol.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -28,7 +28,6 @@
 #include <soc/soc_info.h>
 #include <static.h>
 #include <string.h>
-#include <ux_locales.h>

#define FSP_CLK_NOTUSED			0xFF
 #define FSP_CLK_LAN			0x70
@@ -460,24 +459,8 @@
    	elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
    }

-	if (!vga_init_control)
-		return;
-
-	const char *text = ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
-
-	vbt = cbfs_map("vbt.bin", &vbt_size);
-	if (!vbt) {
-		printk(BIOS_ERR, "Could not load vbt.bin\n");
-		return;
-	}
-
-	printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n");
-
-	m_cfg->VgaInitControl = vga_init_control;
-	m_cfg->VbtPtr = (efi_uintn_t)vbt;
-	m_cfg->VbtSize = vbt_size;
-	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
-	m_cfg->VgaMessage = (efi_uintn_t)text;
+	if (vga_init_control)
+		fsp_set_esol_params(vga_init_control, m_cfg);
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 9691b10..d375185 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -8,12 +8,12 @@
 #include <fsp/fsp_debug_event.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
+#include <soc/intel/common/fsp_esol.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <static.h>
-#include <ux_locales.h>

#define FSP_CLK_NOTUSED		0xff
 #define FSP_CLK_LAN		0x70
@@ -369,29 +369,15 @@
 {
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
    FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd;
-	void *vbt;
-	size_t vbt_size;

if (arch_upd->NvsBufferPtr)
    	return;

-	/* To enhance the user experience, let's display on-screen guidance during memory
-	   training, acknowledging that the process may require patience. */
-
-	vbt = cbfs_map("vbt.bin", &vbt_size);
-	if (!vbt) {
-		printk(BIOS_ERR, "Could not load vbt.bin\n");
-		return;
-	}
-
-	printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n");
    elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);

-	m_cfg->VgaInitControl = 1;
-	m_cfg->VbtPtr = (efi_uintn_t)vbt;
-	m_cfg->VbtSize = vbt_size;
-	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
-	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
+	/* To enhance the user experience, let's display on-screen guidance during memory
+	   training, acknowledging that the process may require patience. */
+	fsp_set_esol_params(1, m_cfg);
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)