[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Configure Acoustic noise mitigation

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79323?usp=email )

Change subject: mb/google/rex/var/screebo: Configure Acoustic noise mitigation
......................................................................

mb/google/rex/var/screebo: Configure Acoustic noise mitigation

Enable Acoustic noise mitigation for google/screebo and set slew rate
to 1/8 for IA domain and ignore the slew rate for SA domain.

BUG=b:312405633,
TEST=Able to build and boot google/screebo.

Before:

[SPEW ]   AcousticNoiseMitigation : 0x0
[SPEW ]   FastPkgCRampDisable for Index = 0 : 0x0
[SPEW ]   SlowSlewRate for Index = 0 : 0x0

After:

[SPEW ]   AcousticNoiseMitigation : 0x1
[SPEW ]   FastPkgCRampDisable for Index = 0 : 0x1
[SPEW ]   SlowSlewRate for Index = 0 : 0x2

Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/rex/variants/screebo/overridetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/79323/1

diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index 8be0e85..0d9984f 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -90,6 +90,15 @@
    	[PchSerialIoIndexI2C5] = PchSerialIoPci,
    }"

+	# Acoustic Noise settings and slew rate configuration:
+	#  slew rate for IA Domain: Fast/8
+	#  Ignore slew rate configuration for SA Domain
+	register "enable_acoustic_noise_mitigation" = "1"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_IA]" = "1"
+	register "slow_slew_rate_config[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate_config[VR_DOMAIN_SA]" = "SLEW_IGNORE"
+
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |