Patch set updated for coreboot: c6cc20c imgtec/pistachio: Add comment on the unusual memory layout
Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10039
-gerrit
commit c6cc20cad3eac18a6f968906a975b11afcb66f94 Author: Patrick Georgi pgeorgi@chromium.org Date: Thu Apr 30 11:38:13 2015 +0200
imgtec/pistachio: Add comment on the unusual memory layout
To avoid having to dig up the constraints again, document the memory layout right in memlayout.ld.
Change-Id: I298cc880ae462f5b197ab2f64beb2f0e0d9f5a7d Signed-off-by: Patrick Georgi pgeorgi@chromium.org --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index e9f6c59..bc67447 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -42,7 +42,10 @@ SECTIONS PRERAM_CBFS_CACHE(0x1a00e000, 72K) SRAM_END(0x1a020000)
- /* Bootblock executes out of KSEG0 and sets up the identity mapping. */ + /* Bootblock executes out of KSEG0 and sets up the identity mapping. + * This is identical to SRAM above, and thus also limited 64K and + * needs to avoid conflicts with items set up above. + */ BOOTBLOCK(0x9a000000, 20K)
/*
-
Patrick Georgi