Attention is currently required from: Zheng Bao. Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/63185
to review the following change.
Change subject: util/amdfwtool: add Sabrina SoC type ......................................................................
util/amdfwtool: add Sabrina SoC type
Add PLATFORM_SABRINA to the enum of supported platforms and integrate it into the existing code.
Signed-off-by: Zheng Bao fishbaozi@gmail.com Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Ibe52b44395619f697686bd900a522562abbe7646 --- M util/amdfwtool/amdfwtool.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/63185/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index c425676..cdee270 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -558,6 +558,7 @@ PLATFORM_CEZANNE, PLATFORM_MENDOCINO, PLATFORM_LUCIENNE, + PLATFORM_SABRINA, };
static uint32_t get_psp_id(enum platform soc_id) @@ -576,6 +577,7 @@ psp_id = 0xBC0C0140; break; case PLATFORM_MENDOCINO: + case PLATFORM_SABRINA: psp_id = 0xBC0D0900; break; case PLATFORM_STONEYRIDGE: @@ -1406,6 +1408,7 @@ case PLATFORM_LUCIENNE: case PLATFORM_CEZANNE: case PLATFORM_MENDOCINO: + case PLATFORM_SABRINA: amd_romsig->efs_gen.gen = EFS_SECOND_GEN; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; @@ -1448,6 +1451,8 @@ return PLATFORM_RENOIR; else if (!strcasecmp(soc_name, "Lucienne")) return PLATFORM_LUCIENNE; + else if (!strcasecmp(soc_name, "Sabrina")) + return PLATFORM_SABRINA; else return PLATFORM_UNKNOWN;
@@ -1900,6 +1905,7 @@ amd_romsig->bios3_entry = BUFF_TO_RUN(ctx, biosdir); break; case PLATFORM_MENDOCINO: + case PLATFORM_SABRINA: break; case PLATFORM_STONEYRIDGE: case PLATFORM_RAVEN: