Change in coreboot[master]: mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34181 )
Change subject: mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L) ......................................................................
mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since it needs to trigger on both edges. With GPIO IRQ, it is necessary to configure the trigger type in coreboot to match the ACPI configuration. This is because: 1. ACPI configuration is used by intel-pinctrl driver in Linux kernel to re-configure the trigger type for the pad in GPIO DW0 config register. This is done when kernel driver probes and requests irq for its device. 2. On resume from S3, the pad configuration gets reset and coreboot sets the trigger type to LEVEL. However, kernel driver does not probe again. This results in the trigger type being configured incorrectly.
This change updates the GPIO configuration for GPP_H0 to set the same trigger type as advertised in ACPI for the kernel.
BUG=b:132672011 TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0 works fine on boot as well as after suspend/resume.
Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/34181/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 1da3d75..a466972 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -329,7 +329,7 @@ /* * H0 : HP_INT_L */ - PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, EDGE_BOTH), /* H1 : CNV_RF_RESET_L */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* H2 : CNV_CLKREQ0 */
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34181 )
Change subject: mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L) ......................................................................
Patch Set 1: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34181 )
Change subject: mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L) ......................................................................
Patch Set 1: Code-Review+2
Good find Furquan!
Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34181 )
Change subject: mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L) ......................................................................
Patch Set 1: Code-Review+1
Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34181 )
Change subject: mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L) ......................................................................
mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since it needs to trigger on both edges. With GPIO IRQ, it is necessary to configure the trigger type in coreboot to match the ACPI configuration. This is because: 1. ACPI configuration is used by intel-pinctrl driver in Linux kernel to re-configure the trigger type for the pad in GPIO DW0 config register. This is done when kernel driver probes and requests irq for its device. 2. On resume from S3, the pad configuration gets reset and coreboot sets the trigger type to LEVEL. However, kernel driver does not probe again. This results in the trigger type being configured incorrectly.
This change updates the GPIO configuration for GPP_H0 to set the same trigger type as advertised in ACPI for the kernel.
BUG=b:132672011 TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0 works fine on boot as well as after suspend/resume.
Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181 Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Sathya Prakash M R sathya.prakash.m.r@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Sathya Prakash M R: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 1da3d75..a466972 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -329,7 +329,7 @@ /* * H0 : HP_INT_L */ - PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, EDGE_BOTH), /* H1 : CNV_RF_RESET_L */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* H2 : CNV_CLKREQ0 */
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Furquan Shaikh (Code Review) -
Paul Fagerburg (Code Review)
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Sathya Prakash M R (Code Review)
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Tim Wawrzynczak (Code Review)