Andrey Petrov (andrey.petrov@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13360
-gerrit
commit 835e44b38aacde8b7dc7f26e30f94aa8ef3c4151 Author: Andrey Petrov andrey.petrov@intel.com Date: Fri Jan 15 18:05:12 2016 -0800
soc/apollolake: Add memory and reserve MMIO resources
This adds most important MMIO reserved memory resources, real DRAM memory resources, and some DRAM resources that can not be used as RAM for whatever reason.
Change-Id: Id5a80cf18d67ace991e8046fa46c4b7ed47c626a Signed-off-by: Andrey Petrov andrey.petrov@intel.com --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/northbridge.c | 143 +++++++++++++++++++++++++++++++++ 2 files changed, 144 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 8581607..4e05726 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -33,6 +33,7 @@ ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c +ramstage-y += northbridge.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c new file mode 100644 index 0000000..efea23b --- /dev/null +++ b/src/soc/intel/apollolake/northbridge.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov andrey.petrov@intel.com for Intel Corp.) + * (Written by Alexandru Gagniuc alexandrux.gagniuc@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <soc/iomap.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/northbridge.h> +#include <soc/pci_ids.h> + +static uint32_t get_bar(device_t dev, unsigned int index) +{ + uint32_t bar; + + bar = pci_read_config32(dev, index); + + /* If not enabled return 0 else strip enabled bit */ + return (bar & 1) ? (bar & ~1) : 0; +} + +static int mc_add_fixed_mmio_resources(device_t dev, int index) +{ + struct resource *res; + + /* PCI extended config region */ + res = new_resource(dev, index++); + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + /* only last 4 bits encode BAR */ + res->base = get_bar(dev, PCIEXBAR) & 0xf0000000; + res->size = PCIEX_SIZE; + + /* Memory Controller HUB */ + res = new_resource(dev, index++); + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + /* BITS 31:15 encode BAR */ + res->base = get_bar(dev, MCHBAR) & 0xffff8000; + res->size = MCH_BASE_SIZE; + return index; +} + + +static int mc_add_dram_resources(device_t dev, int index) +{ + unsigned long base_k, size_k; + uint32_t bgsm, bdsm, tolud, tseg; + uint64_t touud; + struct resource *resource; + + bgsm = ALIGN_DOWN(pci_read_config32(dev, BGSM), MiB); + bdsm = ALIGN_DOWN(pci_read_config32(dev, BDSM), MiB); + tolud = ALIGN_DOWN(pci_read_config32(dev, TOLUD), MiB); + tseg = ALIGN_DOWN(pci_read_config32(dev, TSEG), MiB); + + /* TOUUD is naturally a 64 bit integer */ + touud = ALIGN_DOWN(pci_read_config32(dev, TOUUD), MiB); + touud |= (uint64_t)pci_read_config32(dev, TOUUD + + sizeof(uint32_t)) << 32; + + /* 0 - > 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */ + ram_resource(dev, index++, 0, 640); + + /* 0xc0000 -> top_of_ram, skipping the legacy VGA region */ + base_k = 768; + size_k = (tseg >> 10) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* TSEG -> BGSM */ + resource = new_resource(dev, index++); + resource->base = tseg; + resource->size = bgsm - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; + + /* BGSM -> BDSM */ + resource = new_resource(dev, index++); + resource->base = bgsm; + resource->size = bdsm - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + + /* BDSM -> TOLUD */ + resource = new_resource(dev, index++); + resource->base = bdsm; + resource->size = tolud - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + + /* 4G -> TOUUD */ + base_k = 4ULL*GiB >> 10; + size_k = (touud >> 10) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_resource(dev, index++, 640, 128); + + /* 0xe0000 - 0xfffff: PAM area */ + reserved_ram_resource(dev, index++, 768, 256); + + return index; +} + +static void northbridge_read_resources(device_t dev) +{ + + int index = 0; + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* Add all fixed MMIO resources. */ + index = mc_add_fixed_mmio_resources(dev, index); + + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev, index); +} + +static struct device_operations northbridge_ops = { + .read_resources = northbridge_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = DEVICE_NOOP, + .enable = DEVICE_NOOP +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &northbridge_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEV_ID_APOLLOLAKE_NB +};
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Andrey Petrov