[S] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Gareth Yu, Gareth Yu, Jayvik Desai, Kapil Porwal, Lawrence Chang, Nick Vaccaro, Paul Menzel, SH Kim, Simon Yang.

Subrata Banik has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email )

Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
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Patch Set 18:

(1 comment)

File src/mainboard/google/brya/variants/meliks/ramstage.c:

https://review.coreboot.org/c/coreboot/+/86838/comment/d6065674_e010cb5b?usp... :
PS17, Line 20: 0xf
> Yes, hardcoding the MMIO address is possible. The reason is we need to clear the same system memory which is used by GFX before warm boot. However, I have found 2 possible addresses are used for TWL, 0x81000000 or 0xAF000000.  It means that the address can be changed according to different PCI devices. Even only for this project, I can't say the PCI devices are consistent until its EOL. Thought?

Any temp base should be fine and you can also ensure clearing the temp bar at the end of `reset_display_dphy_clock`.

The implementation should be like

1. Read the `igd_mem_base` if zero then `set_igd_mem_base` to 0xAF000000. Set a static variable (bool temp_bar_imp) to track the temp bar allocation.
2. Reset the DPHY
3. Reset the `igd_mem_base` if `temp_bar_imp` is set meaning IGD bar was not implemented and this code sets the IGD bar