Change in coreboot[master]: [WIP] ACPI: Add acpi_reset_gnvs_for_wake()

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held.
Hello Lance Zhao, build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/50004

to look at the new patch set (#6).

Change subject: [WIP] ACPI: Add acpi_reset_gnvs_for_wake()
......................................................................

[WIP] ACPI: Add acpi_reset_gnvs_for_wake()

With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.

TBD: pm1i and gpei are indeces but u64 at places

Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki 
---
M src/acpi/gnvs.c
M src/include/acpi/acpi_gnvs.h
M src/soc/amd/common/block/acpi/pm_state.c
M src/soc/amd/picasso/acpi.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/baytrail/acpi.c
M src/soc/intel/baytrail/ramstage.c
M src/soc/intel/braswell/acpi.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/ramstage.c
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/common/block/acpi/acpi_wake_source.c
M src/soc/intel/elkhartlake/acpi.c
M src/soc/intel/icelake/acpi.c
M src/soc/intel/jasperlake/acpi.c
M src/soc/intel/skylake/acpi.c
M src/soc/intel/tigerlake/acpi.c
19 files changed, 63 insertions(+), 131 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/50004/6