[M] Change in coreboot[main]: mb/amd/birman_plus/devicetree_glinda.cb: Update USB

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84436?usp=email )

Change subject: mb/amd/birman_plus/devicetree_glinda.cb: Update USB
......................................................................

mb/amd/birman_plus/devicetree_glinda.cb: Update USB

Signed-off-by: Maximilian Brune 
Change-Id: Iacf9ab43c337a8b6a7aa5a37eb8a59644fcaeac6
Original-signed-off-by: Satya SreenivasL 
Original-reviewed-by: Anand Vaikar 
Original-reviewed-by: Ritul Guru 
Original-tested-by: Satya Sreenivas L 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84436
Tested-by: build bot (Jenkins) 
Reviewed-by: Ana Carolina Cabral
Reviewed-by: Felix Held 
---
M src/mainboard/amd/birman_plus/devicetree_glinda.cb
1 file changed, 58 insertions(+), 29 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Ana Carolina Cabral: Looks good to me, but someone else must approve
  Felix Held: Looks good to me, approved

diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
index 9e2f4b3..5e92001 100644
--- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb
+++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
@@ -44,13 +44,13 @@
    register "usb_phy_custom" = "1"
    register "usb_phy" = "{
    	.Usb2PhyPort[0] = {
-			.compdistune = 0x3,
+			.compdistune = 0x1,
    		.pllbtune = 0x1,
    		.pllitune = 0x0,
-			.pllptune = 0xe,
-			.sqrxtune = 0x3,
-			.txfslstune = 0x3,
-			.txpreempamptune = 0x2,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
    		.txpreemppulsetune = 0x0,
    		.txrisetune = 0x1,
    		.txvreftune = 0x3,
@@ -58,13 +58,13 @@
    		.txrestune = 0x2,
    	},
    	.Usb2PhyPort[1] = {
-			.compdistune = 0x3,
+			.compdistune = 0x1,
    		.pllbtune = 0x1,
    		.pllitune = 0x0,
-			.pllptune = 0xe,
-			.sqrxtune = 0x3,
-			.txfslstune = 0x3,
-			.txpreempamptune = 0x2,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
    		.txpreemppulsetune = 0x0,
    		.txrisetune = 0x1,
    		.txvreftune = 0x3,
@@ -72,13 +72,13 @@
    		.txrestune = 0x2,
    	},
    	.Usb2PhyPort[2] = {
-			.compdistune = 0x3,
+			.compdistune = 0x1,
    		.pllbtune = 0x1,
    		.pllitune = 0x0,
-			.pllptune = 0xe,
-			.sqrxtune = 0x3,
-			.txfslstune = 0x3,
-			.txpreempamptune = 0x2,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
    		.txpreemppulsetune = 0x0,
    		.txrisetune = 0x1,
    		.txvreftune = 0x3,
@@ -86,13 +86,13 @@
    		.txrestune = 0x2,
    	},
    	.Usb2PhyPort[3] = {
-			.compdistune = 0x3,
+			.compdistune = 0x1,
    		.pllbtune = 0x1,
    		.pllitune = 0x0,
-			.pllptune = 0xe,
-			.sqrxtune = 0x3,
-			.txfslstune = 0x3,
-			.txpreempamptune = 0x2,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
    		.txpreemppulsetune = 0x0,
    		.txrisetune = 0x1,
    		.txvreftune = 0x3,
@@ -100,13 +100,13 @@
    		.txrestune = 0x2,
    	},
    	.Usb2PhyPort[4] = {
-			.compdistune = 0x3,
+			.compdistune = 0x1,
    		.pllbtune = 0x1,
    		.pllitune = 0x0,
-			.pllptune = 0xe,
-			.sqrxtune = 0x3,
-			.txfslstune = 0x3,
-			.txpreempamptune = 0x2,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
    		.txpreemppulsetune = 0x0,
    		.txrisetune = 0x1,
    		.txvreftune = 0x3,
@@ -114,13 +114,41 @@
    		.txrestune = 0x2,
    	},
    	.Usb2PhyPort[5] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[6] = {
    		.compdistune = 0x3,
    		.pllbtune = 0x1,
    		.pllitune = 0x0,
-			.pllptune = 0xe,
-			.sqrxtune = 0x3,
-			.txfslstune = 0x3,
-			.txpreempamptune = 0x2,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[7] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
    		.txpreemppulsetune = 0x0,
    		.txrisetune = 0x1,
    		.txvreftune = 0x3,
@@ -147,6 +175,7 @@
    	},
    	.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
    	.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
+		.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
    }"

register "gpp_clk_config[0]" = "GPP_CLK_REQ"