Change in coreboot[master]: device/dram/ddr2.c: Code re-formating - coreboot-gerrit

15 Nov 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36858 )
Change subject: device/dram/ddr2.c: Code re-formating
......................................................................
device/dram/ddr2.c: Code re-formating
Change-Id: I937aadca21ddaa9ab4ae354c3a1324a222ae0ff6
Signed-off-by: Elyes HAOUAS ehaouas@noos.fr
---
M src/device/dram/ddr2.c
1 file changed, 47 insertions(+), 73 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36858/1

diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index 5319806..299a590 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -12,7 +12,7 @@
  * GNU General Public License for more details.
  */
-/**
+/*
  * @file ddr2.c
  *
  * \brief Utilities for decoding DDR2 SPDs
@@ -29,7 +29,7 @@
  * = DDR2 SPD decoding helpers
  *----------------------------------------------------------------------------*/
-/**
+/*
  * \brief Checks if the DIMM is Registered based on byte[20] of the SPD
  *
  * Tells if the DIMM type is registered or not.
@@ -38,15 +38,15 @@
  */
 int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type)
 {
-	if ((type == SPD_DDR2_DIMM_TYPE_RDIMM)
-			|| (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM)
-			|| (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM))
+	if ((type == SPD_DDR2_DIMM_TYPE_RDIMM) ||
+	    (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM) ||
+	    (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM))
    	return 1;
return 0;
 }
-/**
+/*
  * \brief Calculate the checksum of a DDR2 SPD unique identifier
  *
  * @param spd pointer to raw SPD data
@@ -69,7 +69,7 @@
    return c;
 }
-/**
+/*
  * \brief Calculate the CRC of a DDR2 SPD unique identifier
  *
  * @param spd pointer to raw SPD data
@@ -93,7 +93,7 @@
    return ddr_crc16(id_bytes, 15);
 }
-/**
+/*
  * \brief Return size of SPD.
  *
  * Returns size of SPD. Usually 128 Byte.
@@ -103,7 +103,7 @@
    return MIN(byte0, SPD_SIZE_MAX_DDR2);
 }
-/**
+/*
  * \brief Return size of eeprom.
  *
  * Returns size of eeprom. Usually 256 Byte.
@@ -119,7 +119,7 @@
    return 1 << byte1;
 }
-/**
+/*
  * \brief Return index of MSB set
  *
  * Returns the index of MSB set.
@@ -129,7 +129,7 @@
    return log2(c);
 }
-/**
+/*
  * \brief Decode SPD tck cycle time
  *
  * Decodes a raw SPD data from a DDR2 DIMM.
@@ -156,8 +156,7 @@
    	break;
    case 0xe:
    case 0xf:
-		printk(BIOS_WARNING, "Invalid tck setting. "
-			"lower nibble is 0x%x\n", c & 0xf);
+		printk(BIOS_WARNING, "Invalid tck setting. lower nibble is 0x%x\n", c & 0xf);
    	return CB_ERR;
    default:
    	low = (c & 0xf) * 10;
@@ -167,7 +166,7 @@
    return CB_SUCCESS;
 }
-/**
+/*
  * \brief Decode SPD bcd style timings
  *
  * Decodes a raw SPD data from a DDR2 DIMM.
@@ -186,7 +185,7 @@
    return CB_SUCCESS;
 }
-/**
+/*
  * \brief Decode SPD tRP, tRRP cycle time
  *
  * Decodes a raw SPD data from a DDR2 DIMM.
@@ -202,7 +201,7 @@
    return ((high * 100 + low) << 8) / 100;
 }
-/**
+/*
  * \brief Decode SPD tRR time
  *
  * Decodes a raw SPD data from a DDR2 DIMM.
@@ -236,7 +235,7 @@
    return CB_SUCCESS;
 }
-/**
+/*
  * \brief Decode SPD tRC,tRFC time
  *
  * Decodes a raw SPD data from a DDR2 DIMM.
@@ -301,7 +300,7 @@
    *tRFC = (*tRFC << 8) / 100;
 }
-/**
+/*
  * \brief Decode the raw SPD data
  *
  * Decodes a raw SPD data from a DDR2 DIMM, and organizes it into a
@@ -348,9 +347,8 @@
reg8 = spd[62];
    if ((reg8 & 0xf0) != 0x10) {
-		printk(BIOS_WARNING,
-			"ERROR: Unsupported SPD revision %01x.%01x\n",
-			reg8 >> 4, reg8 & 0xf);
+		printk(BIOS_WARNING, "ERROR: Unsupported SPD revision %01x.%01x\n", reg8 >> 4,
+		       reg8 & 0xf);
    	dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
    	return SPD_STATUS_INVALID;
    }
@@ -368,18 +366,15 @@
dimm->row_bits = spd[3];
    printram("  Rows               : %u\n", dimm->row_bits);
-	if ((dimm->row_bits > 31) ||
-	    ((dimm->row_bits > 15) && (dimm->rev < 0x13))) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid number of memory rows\n");
+	if ((dimm->row_bits > 31) || ((dimm->row_bits > 15) && (dimm->rev < 0x13))) {
+		printk(BIOS_WARNING, "SPD decode: invalid number of memory rows\n");
    	ret = SPD_STATUS_INVALID_FIELD;
    }
dimm->col_bits = spd[4];
    printram("  Columns            : %u\n", dimm->col_bits);
    if (dimm->col_bits > 15) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid number of memory columns\n");
+		printk(BIOS_WARNING, "SPD decode: invalid number of memory columns\n");
    	ret = SPD_STATUS_INVALID_FIELD;
    }
@@ -403,8 +398,7 @@
    dimm->banks = spd[17];
    printram("  Banks              : %u\n", dimm->banks);
    if (!dimm->banks) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid module banks count\n");
+		printk(BIOS_WARNING, "SPD decode: invalid module banks count\n");
    	ret = SPD_STATUS_INVALID_FIELD;
    }
@@ -440,20 +434,17 @@
dimm->cas_supported = spd[18];
    if ((dimm->cas_supported & 0x3) || !dimm->cas_supported) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid CAS support advertised.\n");
+		printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n");
    	ret = SPD_STATUS_INVALID_FIELD;
    }
    printram("  Supported CAS mask : 0x%x\n", dimm->cas_supported);
if ((dimm->rev < 0x13) && (dimm->cas_supported & 0x80)) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid CAS support advertised.\n");
+		printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n");
    	ret = SPD_STATUS_INVALID_FIELD;
    }
    if ((dimm->rev < 0x12) && (dimm->cas_supported & 0x40)) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid CAS support advertised.\n");
+		printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n");
    	ret = SPD_STATUS_INVALID_FIELD;
    }
@@ -462,59 +453,43 @@
/* SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X */
    if (spd_decode_tck_time(&dimm->cycle_time[cl], spd[9]) != CB_SUCCESS) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid min tCL for CAS%d\n", cl);
+		printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl);
    	ret = SPD_STATUS_INVALID_FIELD;
    }
    /* SDRAM Access from Clock */
-	if (spd_decode_bcd_time(&dimm->access_time[cl], spd[10])
-			!= CB_SUCCESS) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid min tAC for CAS%d\n", cl);
+	if (spd_decode_bcd_time(&dimm->access_time[cl], spd[10]) != CB_SUCCESS) {
+		printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl);
    	ret = SPD_STATUS_INVALID_FIELD;
    }
if (dimm->cas_supported & (1 << (cl - 1))) {
    	/* Minimum Clock Cycle at CLX-1 */
-		if (spd_decode_tck_time(&dimm->cycle_time[cl - 1], spd[23])
-				!= CB_SUCCESS) {
-			printk(BIOS_WARNING,
-				"SPD decode: invalid min tCL for CAS%d\n",
-				cl - 1);
+		if (spd_decode_tck_time(&dimm->cycle_time[cl - 1], spd[23]) != CB_SUCCESS) {
+			printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl - 1);
    		ret = SPD_STATUS_INVALID_FIELD;
    	}
    	/* Maximum Data Access Time (tAC) from Clock at CLX-1 */
-		if (spd_decode_bcd_time(&dimm->access_time[cl - 1], spd[24])
-				!= CB_SUCCESS) {
-			printk(BIOS_WARNING,
-				"SPD decode: invalid min tAC for CAS%d\n",
-				cl - 1);
+		if (spd_decode_bcd_time(&dimm->access_time[cl - 1], spd[24]) != CB_SUCCESS) {
+			printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl - 1);
    		ret = SPD_STATUS_INVALID_FIELD;
    	}
    }
    if (dimm->cas_supported & (1 << (cl - 2))) {
    	/* Minimum Clock Cycle at CLX-2 */
-		if (spd_decode_tck_time(&dimm->cycle_time[cl - 2], spd[25])
-				!= CB_SUCCESS) {
-			printk(BIOS_WARNING,
-				"SPD decode: invalid min tCL for CAS%d\n",
-				cl - 2);
+		if (spd_decode_tck_time(&dimm->cycle_time[cl - 2], spd[25]) != CB_SUCCESS) {
+			printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl - 2);
    		ret = SPD_STATUS_INVALID_FIELD;
    	}
    	/* Maximum Data Access Time (tAC) from Clock at CLX-2 */
-		if (spd_decode_bcd_time(&dimm->access_time[cl - 2], spd[26])
-				!= CB_SUCCESS) {
-			printk(BIOS_WARNING,
-				"SPD decode: invalid min tAC for CAS%d\n",
-				cl - 2);
+		if (spd_decode_bcd_time(&dimm->access_time[cl - 2], spd[26]) != CB_SUCCESS) {
+			printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl - 2);
    		ret = SPD_STATUS_INVALID_FIELD;
    	}
    }
reg8 = (spd[31] >> 5) | (spd[31] << 3);
    if (!reg8) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid rank density.\n");
+		printk(BIOS_WARNING, "SPD decode: invalid rank density.\n");
    	ret = SPD_STATUS_INVALID_FIELD;
    }
@@ -611,8 +586,7 @@
    printram("  ECC support        : %x\n", dimm->flags.is_ecc);
dimm->flags.stacked = !!(spd[5] & 0x10);
-	printram("  Package            : %s\n",
-	    dimm->flags.stacked ? "stack" : "planar");
+	printram("  Package            : %s\n", dimm->flags.stacked ? "stack" : "planar");
if (spd_size > 71) {
    	memcpy(&dimm->manufacturer_id, &spd[64], 4);
@@ -662,14 +636,14 @@
    printk(BIOS_INFO, "%s%3u.%.3u us\n", msg, mant, fp);
 }
-/**
-* \brief Print the info in DIMM
-*
-* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is
-* selected, or for a purely informative output.
-*
-* @param dimm pointer to already decoded @ref dimm_attr structure
-*/
+/*
+ * \brief Print the info in DIMM
+ *
+ * Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is
+ * selected, or for a purely informative output.
+ *
+ * @param dimm pointer to already decoded @ref dimm_attr structure
+ */
 void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm)
 {
    char buf[32];
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I937aadca21ddaa9ab4ae354c3a1324a222ae0ff6
Gerrit-Change-Number: 36858
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr
Gerrit-MessageType: newchange



    