[S] Change in coreboot[main]: soc/riscv/ucb: Switch to FDT parsing to get memory size

[Joel Bueno (Code Review)]

Attention is currently required from: Joel Bueno, Philipp Hug, ron minnich.

Hello Maximilian Brune, Philipp Hug, build bot (Jenkins), ron minnich,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86588?usp=email

to look at the new patch set (#3).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/riscv/ucb: Switch to FDT parsing to get memory size
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soc/riscv/ucb: Switch to FDT parsing to get memory size

Currently, coreboot tries to manually probe the memory for
the Spike target as part of the SOC_UCB_RISCV target.

However, Spike already passes a pointer to the device tree,
so use it instead to get the memory size (like qemu-riscv does).

TEST=Compile for SPIKE-RISCV and run (cmdline: spike -m1024 build/coreboot.elf)

Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43
Signed-off-by: joel.bueno 
---
M src/soc/ucb/riscv/Kconfig
M src/soc/ucb/riscv/cbmem.c
2 files changed, 10 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/86588/3