Change in coreboot[master]: soc/intel/alderlake: Add lp5_ccc_config to the board memory configura...

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47436 )

Change subject: soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47436/4/src/soc/intel/alderlake/inc... 
File src/soc/intel/alderlake/include/soc/meminit.h:

https://review.coreboot.org/c/coreboot/+/47436/4/src/soc/intel/alderlake/inc... 
PS4, Line 96: CCC
What does CCC stand for? CA, CTL, CLK?