[M] Change in coreboot[master]: soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73713 )

Change subject: soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table
......................................................................

soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table

Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table.

990:CSME ROM started execution                        0
944:CSE sent 'Boot Stall Done' to PMC                 47,000
945:CSE started to handle ICC configuration           225,000 (178,000)
946:CSE sent 'Host BIOS Prep Done' to PMC             225,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC   516,000 (291,000)
991:Die Management Unit (DMU) load completed          587,000 (71,000)
  0:1st timestamp                                     597,427 (10,427)

BUG=b:259366109
TEST=Able to see TS elapse prior to IA reset on Rex

Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571
Signed-off-by: Bora Guvendik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713
Reviewed-by: Subrata Banik 
Reviewed-by: Kapil Porwal 
Tested-by: build bot (Jenkins) 
Reviewed-by: Dinesh Gehlot 
---
M src/soc/intel/common/block/include/intelblocks/cse_telemetry.h
A src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h
M src/soc/intel/meteorlake/Makefile.inc
A src/soc/intel/meteorlake/cse_telemetry.c
M src/soc/intel/meteorlake/romstage/romstage.c
5 files changed, 228 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved
  Dinesh Gehlot: Looks good to me, approved

diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h
index d45b112..291a264 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h
@@ -5,6 +5,8 @@

#if CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1)
 #include "cse_telemetry_v1.h"
+#elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2)
+#include "cse_telemetry_v2.h"
 #endif

#endif // SOC_INTEL_COMMON_CSE_TELEMETRY_H
diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h
new file mode 100644
index 0000000..4acdc31
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H
+#define SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H
+
+enum cse_boot_perf_data_v2 {
+	/* CSME ROM start execution  */
+	PERF_DATA_CSME_ROM_START = 0,
+
+	/* EC Boot Load Done (CSME ROM starts main execution) */
+	PERF_DATA_EC_BOOT_LOAD_DONE = 1,
+
+	/* CSME ROM completed execution / CSME RBE started */
+	PERF_DATA_CSME_ROM_COMPLETED = 2,
+
+	/* CSME got ESE Init Done indication from ESE */
+	PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3,
+
+	/* CSME RBE started SOC.PMC patch and payloads read from SPI flash */
+	PERF_DATA_CSME_RBE_SOC_PMC_PATCH_LOADING_START = 4,
+
+	/* CSME RBE completed SOC.PMC patch and payloads read from SPI flash */
+	PERF_DATA_CSME_RBE_SOC_PMC_PATCH_LOADING_COMPLETED = 5,
+
+	/* CSME RBE started pushing SOC.PMC patch and payloads */
+	PERF_DATA_CSME_RBE_SOC_PMC_PATCH_PUSH_START = 6,
+
+	/* CSME RBE completed pushing SOC.PMC patch and payloads */
+	PERF_DATA_CSME_RBE_SOC_PMC_PATCH_PUSH_COMPLETED = 7,
+
+	/* CSME RBE set "Boot Stall Done" indication to SOC.PMC */
+	PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 8,
+
+	/* CSME RBE Started load IOE.PMC patch and payloads */
+	PERF_DATA_CSME_RBE_IOE_PMC_PATCH_LOADING_START = 9,
+
+	/* CSME RBE completed to load IOE.PMC patch and payloads */
+	PERF_DATA_CSME_RBE_IOE_PMC_PATCH_LOADING_COMPLETED = 10,
+
+	/* CSME RBE jumped to CSME Kernel */
+	PERF_DATA_CSME_RBE_KERNEL_JUMP = 11,
+
+	/* CSME BUP start running  */
+	PERF_DATA_CSME_BUP_START = 12,
+
+	/* CSME established IPC channel communication with ESE */
+	PERF_DATA_CSME_IPC_CHANNEL_FOR_ESE_UP = 13,
+
+	/* ESE FW initialization completed */
+	PERF_DATA_ESE_FW_INIT_DONE = 14,
+
+	/* PMC set PPS */
+	PERF_DATA_PMC_SET_PPS = 15,
+
+	/* CSME got ICC_CFG_START message from PMC */
+	PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC = 16,
+
+	/* PMC got PCH_PWROK */
+	PERF_DATA_PMC_GOT_PCH_PWROK = 17,
+
+	/* CSME set "Host Boot Prep Done" indication to PMC  */
+	PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 18,
+
+	/* CSME starts PHYs loading - phase 1 - USB, PCIe */
+	PERF_DATA_CSME_PHASE1_PHY_LOADING_START = 19,
+
+	/* CSME completed phase 1 PHYs loading - USB, PCIe */
+	PERF_DATA_CSME_PHASE1_PHY_LOADING_COMPLETED = 20,
+
+	/* PMC indicated CSME that xxPWRGOOD was asserted */
+	PERF_DATA_PMC_PWRGOOD_ASSERTED = 21,
+
+	/* PMC indicated CSME that SYS_PWROK was asserted */
+	PERF_DATA_PMC_SYS_PWROK_ASSERTED = 22,
+
+	/* ESE sent IPC message to CSME indicating PUnit load completed */
+	PERF_DATA_ESE_PUNIT_LOAD_COMPLETED = 23,
+
+	/* PMC indicates CSME that xxPLTRST was de-asserted */
+	PERF_DATA_PMC_PLTRST_DEASSERTED = 24,
+
+	/* PMC sent "CPU_BOOT_CONFIG" start message to CSME */
+	PERF_DATA_PMC_CPU_BOOT_CONFIG_START = 25,
+
+	/* CSME starts PHYs loading - phase 2 - UFS */
+	PERF_DATA_CSME_PHASE2_PHY_LOADING_START = 26,
+
+	/* CSME completed phase 2 PHYs loading - UFS */
+	PERF_DATA_CSME_PHASE2_PHY_LOADING_COMPLETED = 27,
+
+	/* CSME sent "CPU_BOOT_CONFIG" done message to PMC */
+	PERF_DATA_CSME_CPU_BOOT_CONFIG_DONE = 28,
+
+	/* PMC sent "Core Reset Done Ack - Sent" message to CSME */
+	PERF_DATA_PMC_SENT_CRDA = 29,
+
+	/* ESE sent IPC message to CSME indicating DMU load completed */
+	PERF_DATA_ESE_DMU_LOAD_COMPLETED = 30,
+
+	/* ACM Active indication - ACM started its execution */
+	PERF_DATA_ACM_START = 31,
+
+	/* ACM Done indication - ACM completed execution */
+	PERF_DATA_ACM_DONE = 32,
+
+	/* BIOS sent "Get_BIOS_Seed" message to CSME */
+	PERF_DATA_BIOS_SEED_MSG_RECEIVED = 33,
+
+	/* CSME responded to "Get_BIOS_Seed" message */
+	PERF_DATA_BIOS_SEED_MSG_REPLIED = 34,
+
+	/* BIOS sent DRAM Init Done message */
+	PERF_DATA_BIOS_DRAM_INIT_DONE = 35,
+
+	/* CSME sent DRAM Init Done message back to BIOS */
+	PERF_DATA_CSME_DRAM_INIT_DONE = 36,
+
+	/* CSME started loading TCSS components (IOM, NPHY, TBT) */
+	PERF_DATA_CSME_LOAD_TCSS_START = 37,
+
+	/* CSME start loading ACE */
+	PERF_DATA_CSME_LOAD_ACE_START = 38,
+
+	/* CSME started loading eDP PHY */
+	PERF_DATA_CSME_LOAD_EDP_PHY_START = 39,
+
+	/* CSME completed loading eDP PHY */
+	PERF_DATA_CSME_LOAD_EDP_PHY_COMPLETED = 40,
+
+	/* BIOS sent "Core BIOS Done" message to CSME */
+	PERF_DATA_BIOS_BIOS_CORE_DONE = 41,
+
+	/* CSME sent "Core BIOS Done" ack message back to BIOS */
+	PERF_DATA_CSME_BIOS_CORE_DONE = 42,
+
+	/* BIOS sent "End Of Post" message to CSME */
+	PERF_DATA_BIOS_END_OF_POST = 43,
+
+	/* CSME sent "End Of Post" ack message back to BIOS */
+	PERF_DATA_CSME_END_OF_POST = 44,
+
+	/* CSME started loading ISH Bringup module */
+	PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START = 45,
+
+	/* CSME completed loading ISH Bringup module */
+	PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE = 46,
+
+	/* CSME started loading ISH Main module */
+	PERF_DATA_CSME_LOAD_ISH_MAIN_START = 47,
+
+	/* CSME completed loading Main module */
+	PERF_DATA_CSME_LOAD_ISH_MAIN_DONE = 48,
+
+	/* CSME reached Transition Complete */
+	PERF_DATA_CSME_TRANSITION_COMPLETE = 49,
+
+	/* 50 - 62 Reserved */
+
+	/* Timestamp when CSME responded to BupGetBootData message itself */
+	PERF_DATA_CSME_GET_PERF_RESPONSE = 63,
+};
+
+#endif // SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H
diff --git a/src/soc/intel/meteorlake/Makefile.inc b/src/soc/intel/meteorlake/Makefile.inc
index 87fb3a3..fd94cda 100644
--- a/src/soc/intel/meteorlake/Makefile.inc
+++ b/src/soc/intel/meteorlake/Makefile.inc
@@ -21,6 +21,7 @@
 bootblock-y += p2sb.c
 bootblock-y += soc_info.c

+romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
 romstage-y += espi.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
diff --git a/src/soc/intel/meteorlake/cse_telemetry.c b/src/soc/intel/meteorlake/cse_telemetry.c
new file mode 100644
index 0000000..7f5d947a
--- /dev/null
+++ b/src/soc/intel/meteorlake/cse_telemetry.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <intelblocks/cse.h>
+#include <timestamp.h>
+
+void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time)
+{
+	s64 start_stamp;
+
+	if (!ts) {
+		printk(BIOS_ERR, "%s: Failed to insert CSME timestamps\n", __func__);
+		return;
+	}
+
+	start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE];
+
+	timestamp_add(TS_ME_ROM_START, start_stamp);
+	timestamp_add(TS_ME_BOOT_STALL_END,
+		start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]);
+	timestamp_add(TS_ME_ICC_CONFIG_START,
+		start_stamp + ts[PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC]);
+	timestamp_add(TS_ME_HOST_BOOT_PREP_END,
+		start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]);
+	timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC,
+		start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]);
+	timestamp_add(TS_ESE_DMU_LOAD_END,
+		start_stamp + ts[PERF_DATA_ESE_DMU_LOAD_COMPLETED]);
+}
diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index 2df3e11..ebb440c 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -134,6 +134,10 @@
    	timestamp_add_now(TS_CSE_FW_SYNC_END);
    }

+	/* Update coreboot timestamp table with CSE timestamps */
+	if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))
+		cse_get_telemetry_data();
+
    /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
    systemagent_early_init();
    /* Program SMBus base address and enable it */