[M] Change in coreboot[main]: soc/amd/common/acpi: Add SPI flash controller

[Felix Held (Code Review)]

Attention is currently required from: Ana Carolina Cabral, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel.

Felix Held has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84918?usp=email )

Change subject: soc/amd/common/acpi: Add SPI flash controller
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Patch Set 5:

(1 comment)

File src/soc/amd/common/acpi/spi.asl:

https://review.coreboot.org/c/coreboot/+/84918/comment/5c5c9c47_ce8ddb7c?usp... :
PS5, Line 21: ASCE
different values get written to this field from the ASSC method when the driver acquires the bus vs when it releases the bus resulting in different spi chip select pins being used; since the spi flash will always use the same chip select pin, this likely breaks functionality in some case; not sure though which exact case