[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT[A-D] to PIRQ using PIR reg...

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[e-mail] has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85012?usp=email )

Change subject: soc/intel/common/block/itss: Route PCI INT[A-D] to PIRQ using PIR registers
......................................................................

soc/intel/common/block/itss: Route PCI INT[A-D] to PIRQ using PIR registers

ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one of
PIRQA-H. This patch adds a funtion `itss_get_pir()` returning PIRQx for a
given device and INT pin.

Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b
Signed-off-by: Yuchi Chen 
---
M src/soc/intel/common/block/include/intelblocks/itss.h
M src/soc/intel/common/block/itss/itss.c
2 files changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/85012/1

diff --git a/src/soc/intel/common/block/include/intelblocks/itss.h b/src/soc/intel/common/block/include/intelblocks/itss.h
index 84ba7b4..e9850a6 100644
--- a/src/soc/intel/common/block/include/intelblocks/itss.h
+++ b/src/soc/intel/common/block/include/intelblocks/itss.h
@@ -23,6 +23,9 @@
 #define PCR_ITSS_PIRQG_ROUT	0x3106
 /* PIRQH Routing Control Register */
 #define PCR_ITSS_PIRQH_ROUT	0x3107
+/* ITSS Interrupt Route */
+#define PCR_ITSS_PIR	0x3140
+#define PCI_ITSS_PIR(i)	(PCR_ITSS_PIR + (i) * 2)
 /* ITSS Interrupt polarity control */
 #define PCR_ITSS_IPC0_CONF	0x3200
 /* ITSS Power reduction control */
@@ -30,6 +33,7 @@

#if !defined(__ACPI__)

+#include <device/device.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 #include <stdint.h>

@@ -43,6 +47,12 @@
 void itss_irq_init(const uint8_t pch_interrupt_routing[PIRQ_COUNT]);
 void itss_clock_gate_8254(void);

+/* SoC implemention to return corresponding PIR register offset. */
+uint32_t itss_soc_get_pir(struct device *dev);
+
+/* Return which PIRQx the device's INTx is connected to. */
+enum pirq itss_get_dev_pirq(struct device *dev, enum pci_pin pin);
+
 #endif /* !defined(__ACPI__) */

#endif /* SOC_INTEL_COMMON_BLOCK_ITSS_H */
diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c
index 50e4c38..83094e2 100644
--- a/src/soc/intel/common/block/itss/itss.c
+++ b/src/soc/intel/common/block/itss/itss.c
@@ -134,3 +134,12 @@

show_irq_polarities("After");
 }
+
+enum pirq itss_get_dev_pirq(struct device *dev, enum pci_pin pin)
+{
+	uint16_t pir = pcr_read16(PID_ITSS, itss_soc_get_pir(dev));
+	/* The lower 3 bits of every 4 bits indicates which PIRQ is connect to INT. */
+	unsigned int pir_shift = (pin - PCI_INT_A) * 4;
+	unsigned int pir_mask = 0x07;
+	return ((pir >> pir_shift) & pir_mask) + PIRQ_A;
+}