[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Update gpio setting

[Jian Tong (Code Review)]

Jian Tong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85966?usp=email )

Change subject: mb/google/brox/var/lotso: Update gpio setting
......................................................................

mb/google/brox/var/lotso: Update gpio setting

For edge trigger,the default is "rising edge"(invert=0),
and it needs to "invert" (invert=1) for falling edge.

BUG=b:359437265
TEST=emerge-brox coreboot chromeos-bootimage
     oscilloscope measurement interrupt is triggered by falling edge

Change-Id: I132b43fd552d2babfbcd497bc6a017f354c69e10
Signed-off-by: Jian Tong 
---
M src/mainboard/google/brox/variants/lotso/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/85966/1

diff --git a/src/mainboard/google/brox/variants/lotso/gpio.c b/src/mainboard/google/brox/variants/lotso/gpio.c
index d5abe8c..ca1eaa8 100644
--- a/src/mainboard/google/brox/variants/lotso/gpio.c
+++ b/src/mainboard/google/brox/variants/lotso/gpio.c
@@ -57,6 +57,8 @@
    /* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0#
     * NF6: USB_C_GPP_F16] ==> GSPI1_SOC_TCHSCR_CS_L */
    PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
+	/* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, EDGE_SINGLE, INVERT),
    /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> MEM_STRAP_0 */
    PAD_CFG_GPI(GPP_S4, NONE, PLTRST),
    /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> MEM_STRAP_1 */
@@ -65,8 +67,6 @@
    PAD_CFG_GPI(GPP_S6, NONE, PLTRST),
    /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_STRAP_3 */
    PAD_CFG_GPI(GPP_S7, NONE, PLTRST),
-	/* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, EDGE_SINGLE, NONE),
 };