Change in coreboot[master]: nb/amd/agesa/family15tn: Use generic allocation functions for PCI domain

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53988 )

Change subject: nb/amd/agesa/family15tn: Use generic allocation functions for PCI domain
......................................................................

nb/amd/agesa/family15tn: Use generic allocation functions for PCI domain

Move the DRAM reporting to read_resoures function before the resources
are being set. Use generic PCI domain resource allocation functions
to read and set domain resources.

TEST=not tested

Signed-off-by: Michał Żygowski 
Change-Id: Icb9c9d6b6d527127282073eb03a6ae9fbd242f5a
---
M src/northbridge/amd/agesa/family15tn/northbridge.c
1 file changed, 4 insertions(+), 52 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/53988/1

diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index d547df3..015475b 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -54,13 +54,6 @@
    printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
 }

-static u32 f1_read_config32(unsigned int reg)
-{
-	if (fx_devs == 0)
-		get_fx_devs();
-	return pci_read_config32(__f1_dev[0], reg);
-}
-
 static void f1_write_config32(unsigned int reg, u32 value)
 {
    int i;
@@ -354,43 +347,6 @@
    .enable_dev = 0,
 };

-static void domain_read_resources(struct device *dev)
-{
-	unsigned int reg;
-
-	/* Find the already assigned resource pairs */
-	get_fx_devs();
-	for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
-		u32 base, limit;
-		base  = f1_read_config32(reg);
-		limit = f1_read_config32(reg + 0x04);
-		/* Is this register allocated? */
-		if ((base & 3) != 0) {
-			unsigned int nodeid, reg_link;
-			struct device *reg_dev;
-			if (reg < 0xc0) { // mmio
-				nodeid = (limit & 0xf) + (base&0x30);
-			} else { // io
-				nodeid =  (limit & 0xf) + ((base>>4)&0x30);
-			}
-			reg_link = (limit >> 4) & 7;
-			reg_dev = __f0_dev[nodeid];
-			if (reg_dev) {
-				/* Reserve the resource  */
-				struct resource *res;
-				res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
-				if (res) {
-					res->flags = 1;
-				}
-			}
-		}
-	}
-	/* FIXME: do we need to check extend conf space?
-	   I don't believe that much preset value */
-
-	pci_domain_read_resources(dev);
-}
-
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 struct hw_mem_hole_info {
    unsigned int hole_startk;
@@ -437,7 +393,7 @@
 }
 #endif

-static void domain_set_resources(struct device *dev)
+static void domain_read_resources(struct device *dev)
 {
    unsigned long mmio_basek;
    u32 pci_tolm;
@@ -448,6 +404,8 @@
    u32 reset_memhole = 1;
 #endif

+	pci_domain_read_resources(dev);
+
    pci_tolm = 0xffffffffUL;
    for (link = dev->link_list; link; link = link->next) {
    	pci_tolm = find_pci_tolm(link);
@@ -527,17 +485,11 @@
    }

add_uma_resource_below_tolm(dev, 7);
-
-	for (link = dev->link_list; link; link = link->next) {
-		if (link->children) {
-			assign_resources(link);
-		}
-	}
 }

static struct device_operations pci_domain_ops = {
    .read_resources	  = domain_read_resources,
-	.set_resources	  = domain_set_resources,
+	.set_resources	  = pci_domain_set_resources,
    .scan_bus	  = pci_domain_scan_bus,
 };