Attention is currently required from: Martin Roth, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51157 )
Change subject: nb/intel/haswell: Finalize northbridge in ramstage ......................................................................
nb/intel/haswell: Finalize northbridge in ramstage
There's no need to finalize the northbridge in SMM.
Change-Id: I8b2c0d14a79e4fcd2e8985ce58542791cef9b1fe Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/Makefile.inc D src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/southbridge/intel/lynxpoint/smihandler.c 5 files changed, 33 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/51157/1
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b2fd530..f718f9a 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -18,8 +18,6 @@ romstage-y += early_init.c romstage-y += report_platform.c
-smm-y += finalize.c - # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c deleted file mode 100644 index b95b3fe..0000000 --- a/src/northbridge/intel/haswell/finalize.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/pci_ops.h> -#include "haswell.h" - -void intel_northbridge_haswell_finalize_smm(void) -{ - pci_or_config16(HOST_BRIDGE, GGC, 1 << 0); - pci_or_config32(HOST_BRIDGE, DPR, 1 << 0); - pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, 1 << 10); - pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0); - pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0); - pci_or_config32(HOST_BRIDGE, TOM, 1 << 0); - pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0); - pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0); - pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0); - pci_or_config32(HOST_BRIDGE, TSEG, 1 << 0); - pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); - - /* Memory Controller Lockdown */ - MCHBAR32(MC_LOCK) |= 0x8f; - - MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ - MCHBAR32_OR(DMIVCLIM, 1 << 31); - MCHBAR32_OR(CRDTLCK, 1 << 0); - MCHBAR32_OR(MCARBLCK, 1 << 0); - MCHBAR32_OR(REQLIM, 1 << 31); - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - - /* Read+write the following */ - MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); - MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); - MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID); -} diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index f158c21..6a99074 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -75,8 +75,6 @@
#ifndef __ASSEMBLER__
-void intel_northbridge_haswell_finalize_smm(void); - void mb_late_romstage_setup(void); /* optional */
void haswell_early_initialization(void); diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 7ccfdb1..ab42e72 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -546,11 +546,44 @@ set_power_limits(28); }
+static void northbridge_final(struct device *dev) +{ + pci_or_config16(dev, GGC, 1 << 0); + pci_or_config32(dev, DPR, 1 << 0); + pci_or_config32(dev, MESEG_LIMIT, 1 << 10); + pci_or_config32(dev, REMAPBASE, 1 << 0); + pci_or_config32(dev, REMAPLIMIT, 1 << 0); + pci_or_config32(dev, TOM, 1 << 0); + pci_or_config32(dev, TOUUD, 1 << 0); + pci_or_config32(dev, BDSM, 1 << 0); + pci_or_config32(dev, BGSM, 1 << 0); + pci_or_config32(dev, TSEG, 1 << 0); + pci_or_config32(dev, TOLUD, 1 << 0); + + /* Memory Controller Lockdown */ + MCHBAR32(MC_LOCK) |= 0x8f; + + MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ + MCHBAR32_OR(DMIVCLIM, 1 << 31); + MCHBAR32_OR(CRDTLCK, 1 << 0); + MCHBAR32_OR(MCARBLCK, 1 << 0); + MCHBAR32_OR(REQLIM, 1 << 31); + MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ + + /* Read+write the following */ + MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); + MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); + MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID); +} + static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, + .final = northbridge_final, .acpi_fill_ssdt = generate_cpu_entries, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index aebc038..8b13f16 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -274,7 +274,6 @@
intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); intel_cpu_haswell_finalize_smm();
chipset_finalized = 1;
-
Angel Pons (Code Review)