Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates

[Furquan Shaikh (Code Review)]

Attention is currently required from: Shreesh Chhabbi.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )

Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
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Patch Set 8:

(1 comment)

File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/49766/comment/a0050c48_1e79d3f0 
PS3, Line 236: LpmStateEnableMask
> Hi Furquan, I did not find the upds for external bypass, external clk gate and external phy gate. […]

Hi Shreesh, I was referring to adding configs for external bypass, external clk and phy gate to `soc_intel_alderlake_config` here: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/alderlake/c...

And then update current boards (tglrvp and volteer) to set these as per their design. Then this function can set the disable mask appropriately. Does that make sense?