Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36339 )
Change subject: soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7 ......................................................................
soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7
Set MSR 0x2e7 in any case at the end of POST to lock most of the chipset BAR registers in accordance to Intel BWG.
Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/finalize.c 5 files changed, 21 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36339/1
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 115b732..17cf4d9 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -19,8 +19,10 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <cpu/x86/mp.h> #include <cpu/x86/smm.h> #include <device/pci.h> +#include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/tco.h> @@ -110,6 +112,9 @@
pch_finalize();
+ /* Lock chipset memory registers to protect SMM */ + mp_run_on_all_cpus(cpu_lt_lock_memory, NULL); + printk(BIOS_DEBUG, "Finalizing SMM.\n"); outb(APM_CNT_FINALIZE, APM_CNT);
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 75e7112..8c3454c 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -320,3 +320,9 @@ (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } } + +/* Lock chipset memory registers to protect SMM */ +void cpu_lt_lock_memory(void) +{ + set_msr_bit(MSR_LT_LOCK_MEMORY, 0); +} diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index a70b5a1..c48449f 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -18,8 +18,10 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <cpu/x86/mp.h> #include <cpu/x86/smm.h> #include <device/pci.h> +#include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/tco.h> @@ -109,6 +111,9 @@
pch_finalize();
+ /* Lock chipset memory registers to protect SMM */ + mp_run_on_all_cpus(cpu_lt_lock_memory, NULL); + printk(BIOS_DEBUG, "Finalizing SMM.\n"); outb(APM_CNT_FINALIZE, APM_CNT);
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 63142b9..9bf2431 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -578,11 +578,5 @@
void cpu_lock_sgx_memory(void) { - msr_t msr; - - msr = rdmsr(MSR_LT_LOCK_MEMORY); - if ((msr.lo & 1) == 0) { - msr.lo |= 1; /* Lock it */ - wrmsr(MSR_LT_LOCK_MEMORY, msr); - } + cpu_lt_lock_memory(); } diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 4cc9c83..58a8701 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -20,6 +20,7 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <cpu/x86/mp.h> #include <cpu/x86/smm.h> #include <device/pci.h> #include <intelblocks/cpulib.h> @@ -123,6 +124,9 @@ reg8 |= SMI_LOCK; pci_write_config8(dev, GEN_PMCON_A, reg8); } + + /* Lock chipset memory registers to protect SMM */ + mp_run_on_all_cpus(cpu_lt_lock_memory, NULL); }
static void soc_finalize(void *unused)
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36339 )
Change subject: soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7 ......................................................................
Uploaded patch set 2.
Hello Patrick Rudolph, Subrata Banik, Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36339
to look at the new patch set (#2).
Change subject: soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7 ......................................................................
soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7
Set MSR 0x2e7 in any case at the end of POST to lock most of the chipset BAR registers in accordance to Intel BWG.
Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/finalize.c 6 files changed, 23 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36339/2
Hello Patrick Rudolph, Subrata Banik, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36339
to look at the new patch set (#3).
Change subject: soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7 ......................................................................
soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7
Set MSR 0x2e7 in any case at the end of POST to lock most of the chipset BAR registers in accordance to Intel BWG.
Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/finalize.c 6 files changed, 24 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36339/3
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36339 )
Change subject: soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7 ......................................................................
Uploaded patch set 3.
Hello Patrick Rudolph, Subrata Banik, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36339
to look at the new patch set (#4).
Change subject: soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7 ......................................................................
soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7
Set MSR 0x2e7 in any case at the end of POST to lock most of the chipset BAR registers in accordance to Intel BWG.
Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/finalize.c 7 files changed, 26 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36339/4
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36339 )
Change subject: soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7 ......................................................................
Uploaded patch set 4.
Hello Patrick Rudolph, Subrata Banik, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36339
to look at the new patch set (#5).
Change subject: soc/intel/common: add common function to set LT_LOCK_MEMORY ......................................................................
soc/intel/common: add common function to set LT_LOCK_MEMORY
Add a common function for setting LT_LOCK_MEMORY via MSR 0x2E7, which locks most of the chipset BAR registers in accordance to Intel BWG.
Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/msr.h 3 files changed, 11 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36339/5
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36339 )
Change subject: soc/intel/common: add common function to set LT_LOCK_MEMORY ......................................................................
Uploaded patch set 5.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36339 )
Change subject: soc/intel/common: add common function to set LT_LOCK_MEMORY ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36339/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/36339/5/src/soc/intel/common/block/... PS5, Line 326: msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT); does it crash if lock bit is set twice?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36339 )
Change subject: soc/intel/common: add common function to set LT_LOCK_MEMORY ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36339/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/36339/5/src/soc/intel/common/block/... PS5, Line 326: msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT);
does it crash if lock bit is set twice?
it isn't, msr_set_bit checks that
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36339 )
Change subject: soc/intel/common: add common function to set LT_LOCK_MEMORY ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36339 )
Change subject: soc/intel/common: add common function to set LT_LOCK_MEMORY ......................................................................
soc/intel/common: add common function to set LT_LOCK_MEMORY
Add a common function for setting LT_LOCK_MEMORY via MSR 0x2E7, which locks most of the chipset BAR registers in accordance to Intel BWG.
Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/36339 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/msr.h 3 files changed, 11 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 75e7112..71e4dbf 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -23,10 +23,10 @@ #include <arch/cpu.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/msr.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pm.h> -#include <intelblocks/msr.h> #include <soc/pci_devs.h> #include <stdint.h>
@@ -320,3 +320,8 @@ (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } } + +void cpu_lt_lock_memory(void *unused) +{ + msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 8630fd1..1aa88e1 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -161,4 +161,7 @@ /* Configure Machine Check Architecture support */ void mca_configure(void);
+/* Lock chipset memory registers to protect SMM */ +void cpu_lt_lock_memory(void *unused); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 6fdf26e..3e67fd7 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -67,6 +67,8 @@ #define MSR_POWER_CTL 0x1fc #define POWER_CTL_C1E_MASK (1 << 1) #define MSR_EVICT_CTL 0x2e0 +#define MSR_LT_CONTROL 0x2e7 +#define LT_CONTROL_LOCK_BIT (0) #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 #define SMM_FEATURE_CONTROL_MSR 0x4e0
-
Michael Niewöhner (Code Review) -
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)