[XS] Change in coreboot[main]: soc/intel/pantherlake: Update FSPM Trace parameters

[Subrata Banik (Code Review)]

Attention is currently required from: Bora Guvendik, Intel coreboot Reviewers, Jamie Ryu, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Sowmya Aralguppe, Vikrant L Jadeja, Wonkyu Kim.

Subrata Banik has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/85614?usp=email )

Change subject: soc/intel/pantherlake: Update FSPM Trace parameters
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Patch Set 1:

(2 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/85614/comment/7e270d49_5e9b8716?usp... :
PS1, Line 97: 	select SOC_INTEL_DEBUG_CONSENT # TODO: Remove the safe setting for ES SoC
we need to revert the CL which is better for the git history

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/85614/comment/f8c0c65f_f0e8e63d?usp... :
PS1, Line 254: 	m_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG);
i don't see a need to do this because `SOC_INTEL_COMMON_BLOCK_TRACEHUB` is default enabled but if you still wish to do this then better submit a separate CL