Subrata Banik (subrata.banik@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18510
-gerrit
commit d3eb954621a79a1728da67587c133e6e1821efc7 Author: Subrata Banik subrata.banik@intel.com Date: Mon Feb 27 15:47:27 2017 +0530
soc/intel/skylake: Clean up CPU code
Refer all MSRs from common x86/msr.h location.
Change-Id: Ifb73c42fa3f1b0a5bcf076ff768cd7f8d1524b07 Signed-off-by: Subrata Banik subrata.banik@intel.com --- src/soc/intel/skylake/bootblock/cache_as_ram.S | 19 +++----- src/soc/intel/skylake/bootblock/cpu.c | 2 +- src/soc/intel/skylake/cpu.c | 2 +- src/soc/intel/skylake/include/soc/msr.h | 61 -------------------------- 4 files changed, 9 insertions(+), 75 deletions(-)
diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S index 3f8f0f0..0876afe 100644 --- a/src/soc/intel/skylake/bootblock/cache_as_ram.S +++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S @@ -16,16 +16,11 @@
#include <cpu/x86/cache.h> #include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> #include <rules.h>
-#define IA32_PQR_ASSOC 0x0c8f -#define IA32_L3_MASK_1 0x0c91 -#define IA32_L3_MASK_2 0x0c92 -#define CACHE_INIT_VALUE 0 -#define MSR_EVICT_CTL 0x2e0 - .global bootblock_pre_c_entry bootblock_pre_c_entry:
@@ -188,7 +183,7 @@ find_llc_subleaf: */ shl %cl, %eax subl $0x02, %eax - movl $IA32_L3_MASK_1, %ecx + movl $MSR_IA32_L3_MASK_1, %ecx xorl %edx, %edx wrmsr /* @@ -197,12 +192,12 @@ find_llc_subleaf: * For SKL SOC, data size remains 256K consistently. * Hence, creating 1-way associative cache for Data */ - mov $IA32_L3_MASK_2, %ecx + mov $MSR_IA32_L3_MASK_2, %ecx mov $0x01, %eax xorl %edx, %edx wrmsr /* - * Set IA32_PQR_ASSOC = 0x02 + * Set MSR_IA32_PQR_ASSOC = 0x02 * * Possible values: * 0: Default value, no way mask should be applied @@ -210,7 +205,7 @@ find_llc_subleaf: * 2: Apply way mask 2 to LLC * 3: Shouldn't be use in NEM Mode */ - movl $IA32_PQR_ASSOC, %ecx + movl $MSR_IA32_PQR_ASSOC, %ecx movl $0x02, %eax xorl %edx, %edx wrmsr @@ -218,15 +213,15 @@ find_llc_subleaf: movl $CONFIG_DCACHE_RAM_BASE, %edi movl $CONFIG_DCACHE_RAM_SIZE, %ecx shr $0x02, %ecx - movl $CACHE_INIT_VALUE, %eax cld + xor %eax, %eax rep stosl /* * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. * i.e. way 0 is protected from eviction. */ - movl $IA32_PQR_ASSOC, %ecx + movl $MSR_IA32_PQR_ASSOC, %ecx movl $0x01, %eax xorl %edx, %edx wrmsr diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 3cea8bd..c6ede53 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -126,7 +126,7 @@ void set_max_freq(void) }
perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); + wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index d1a684c..6a8f48f 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -409,7 +409,7 @@ static int get_cpu_count(void) int num_threads; int num_cores;
- msr = rdmsr(CORE_THREAD_COUNT_MSR); + msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 4d295e1..62c8cf0 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -18,30 +18,9 @@ #define _SOC_MSR_H_
#define MSR_PIC_MSG_CONTROL 0x2e -#define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_FEATURE_CONFIG 0x13c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 -#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MISC_PWR_MGMT_ISST_EN (1 << 6) -#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) -#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 @@ -51,52 +30,12 @@ #define EMRR_PHYS_BASE_MSR 0x1f4 #define EMRR_PHYS_MASK_MSR 0x1f5 #define IA32_PLATFORM_DCA_CAP 0x1f8 -#define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 -#define IA32_MC0_STATUS 0x401 -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - -#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a -#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b -#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c -#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 -#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 -#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) -#define MSR_COUNTER_24_MHZ 0x637 - -/* long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_DDR_RAPL_LIMIT 0x618 #define MSR_VR_MISC_CONFIG2 0x636 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 - -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c
/* SMM save state MSRs */ #define SMBASE_MSR 0xc20
-
Subrata Banik