[S] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21

[Jérémy Compostella (Code Review)]

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik.

Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85781?usp=email

to look at the new patch set (#3).

The following approvals got outdated and were removed:
Code-Review+2 by Kapil Porwal, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)

The change is no longer submittable: Code-Review and Verified are unsatisfied now.

Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21
......................................................................

soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21

Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8
"Other Device ID" specifies that the first Thunderbolt PCIe root port
number is 21.

The previous offset of 0x10, inherited from Meteor Lake code, caused
an issue that resulted in:

- Temporary deactivation of Thunderbolt PCI devices during ramstage

- Failure to generate critical ACPI SSDT power management data for the
  port

This error led to instability in PCIe tunneling during power state
transitions.

Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2
Signed-off-by: Jeremy Compostella 
---
M src/soc/intel/pantherlake/pcie_rp.c
1 file changed, 7 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/85781/3