[XS] Change in coreboot[main]: soc/intel/tigerlake: Change the maximum C state to C8

[Sean Rhodes (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Nick Vaccaro, Sean Rhodes, Subrata Banik.

Hello Intel coreboot Reviewers, Jérémy Compostella, Nick Vaccaro, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86199?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Change the maximum C state to C8
......................................................................

soc/intel/tigerlake: Change the maximum C state to C8

The EDS says that Tiger Lake "supports C0, C2, C3, C6, C8,
and C10 package states". Update the highest state for non-S0ix
boards accordingly.

Change-Id: I3fe0f5a8f9b52a44d1951037d74df4a244ba602e
Signed-off-by: Sean Rhodes 
---
M src/soc/intel/tigerlake/acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/86199/2