[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email )

(

22 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
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soc/intel/pantherlake: Display Sign-of-Life during memory training

This commit activates the Firmware Support Package (FSP) Memory
Sign-of-Life feature (FSP_UGOP_EARLY_SIGN_OF_LIFE), which allows for the
display of a user-configurable text message on-screen during memory
initialization. This feature enhances the user experience by providing
reassurance that the memory training process is underway and may take
some time.

The following FSP-M UPDs (Updateable Product Data) are utilized:

- VgaInitControl (boolean): Initializes graphics, establishes VGA text
  mode, and centers the VgaMessage text on the screen. It clears the
  screen, disables VGA text mode, and deactivates graphics upon exiting
  the FSP-M (Firmware Support Package - Memory Initialization).

- VbtPtr (address): This is a pointer to the VBT (Video BIOS Table)
  binary.

- VbtSize (unsigned integer): Indicates the size of the VBT binary.

- LidStatus (boolean): Given the limited resources available at early
  boot stages, the text message is shown on a single monitor. The lid
  status determines the most appropriate display to use:

- 0: If the lid is closed, display the text message on an external
       display if one is available; otherwise, display nothing.

- 1: If the lid is open, display the message on the internal display;
       if unavailable, default to an external display.

- VgaMessage (string): Specifies the text message to be displayed.

When the FSP_UGOP_EARLY_SIGN_OF_LIFE flag is set, coreboot is configured
to use the UPDs mentioned above to show a text message during the memory
training phase. This text message can be customized through the locale
text mechanism using the identifier memory_training_desc.

In addition, the newly introduced code records an extra event to
indicate when early Sign-Of-Life has been requested, to cover the Memory
Reference Code (MRC) training scenario. This event logging is crucial
for debugging and analyzing the boot process, especially in production
environments where it helps in pinpointing the exact stage where a boot
issue might occur.

TEST="Enabling FSP-M Sign-of-Life" message is present in the log upon
     the first boot, and a message is displayed on the screen while the
     FSP performs MRC training.

Signed-off-by: Anil Kumar 
Signed-off-by: Jeremy Compostella 
Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85454
Reviewed-by: Ronak Kanabar 
Reviewed-by: Karthik Ramasubramanian 
Tested-by: build bot (Jenkins) 
Reviewed-by: Kapil Porwal 
Reviewed-by: Subrata Banik 
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/romstage/fsp_params.c
2 files changed, 37 insertions(+), 0 deletions(-)

Approvals:
  Karthik Ramasubramanian: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Kapil Porwal: Looks good to me, approved
  Ronak Kanabar: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index df95e52..a54f0de 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -17,6 +17,7 @@
    select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
    select FSP_COMPRESS_FSP_S_LZ4
    select FSP_M_XIP
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
    select FSP_USES_CB_DEBUG_EVENT_HANDLER
    select FSPS_HAS_ARCH_UPD
    select GENERIC_GPIO_LIB
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 0c17d02..8de99d2 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <bootmode.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/msr.h>
+#include <elog.h>
 #include <fsp/debug.h>
 #include <fsp/fsp_debug_event.h>
 #include <fsp/util.h>
@@ -11,6 +13,7 @@
 #include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <static.h>
+#include <ux_locales.h>

#define FSP_CLK_NOTUSED		0xff
 #define FSP_CLK_LAN		0x70
@@ -355,6 +358,35 @@
    fsp_control_log_level(mupd, fsp_debug_enable);
 }

+static void fill_fspm_sign_of_life(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd;
+	void *vbt;
+	size_t vbt_size;
+
+	if (arch_upd->NvsBufferPtr)
+		return;
+
+	/* To enhance the user experience, let's display on-screen guidance during memory
+	   training, acknowledging that the process may require patience. */
+
+	vbt = cbfs_map("vbt.bin", &vbt_size);
+	if (!vbt) {
+		printk(BIOS_ERR, "Could not load vbt.bin\n");
+		return;
+	}
+
+	printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n");
+	elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);
+
+	m_cfg->VgaInitControl = 1;
+	m_cfg->VbtPtr = (efi_uintn_t)vbt;
+	m_cfg->VbtSize = vbt_size;
+	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
+	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
+}
+
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
    const struct soc_intel_pantherlake_config *config = config_of_soc();
@@ -363,6 +395,10 @@
    	fill_fsp_event_handler(mupd);

soc_memory_init_params(&mupd->FspmConfig, config);
+
+	if (CONFIG(FSP_UGOP_EARLY_SIGN_OF_LIFE))
+		fill_fspm_sign_of_life(mupd);
+
    mainboard_memory_init_params(mupd);
 }