Change in ...coreboot[master]: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses
Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32473
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses
Change-Id: I8bf81637f582373d9bba1d47fe5205d459151f3e Signed-off-by: cyrevolt --- M Documentation/northbridge/intel/haswell/mrc.bin.md 1 file changed, 77 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32473/1
diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md index 36ab4c4..7f8d3ca 100644 --- a/Documentation/northbridge/intel/haswell/mrc.bin.md +++ b/Documentation/northbridge/intel/haswell/mrc.bin.md @@ -27,6 +27,83 @@ Alternatively, place `mrc.bin` anywhere you want, and set `MRC_FILE` to its location when building coreboot.
+## SPD Addresses + +When porting a board from vendor firmware, the SPD addresses can be obtained +through `i2c-tools`, which can be found in many GNU/Linux distributions. A more +[detailed description](https://hannuhartikainen.fi/blog/hacking-ddr3-spd/) of +the procedure and beyond can be found in +[Hannu Hartikainen's blog](https://hannuhartikainen.fi). + +First load the kernel modules: + +```bash +modprobe i2c-dev +modprobe eeprom +``` + +Find the SMBus and the addresses of the DIMM's EEPROMs (example output): +```bash +$ decode-dimms | grep Decoding +Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0050 +Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0052 +``` + +Alternatively, look at the sys filesystem: +```bash +$ ls -l /sys/bus/i2c/drivers/eeprom/ +total 0 +lrwxrwxrwx 1 root root 0 Apr 4 01:46 6-0050 -> ../../../../devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/i2c-6/6-0050/ +lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0050 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0050/ +lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0052 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0052/ +--w------- 1 root root 4096 Apr 4 01:47 bind +lrwxrwxrwx 1 root root 0 Apr 4 01:47 module -> ../../../../module/eeprom/ +--w------- 1 root root 4096 Apr 4 01:46 uevent +--w------- 1 root root 4096 Apr 4 01:47 unbind +``` + +The correct I2C bus is 7 in this case, and the EEPROMs are at `0x50` and `0x52`. +Note that the above values are actually hex values. + +You can check the correctness of the SMBus and the addresses of the EEPROMs via +`i2cdetect`: + +```bash +$ i2cdetect -l +i2c-3 unknown i915 gmbus dpc N/A +i2c-1 unknown i915 gmbus vga N/A +i2c-6 unknown DPDDC-A N/A +i2c-4 unknown i915 gmbus dpb N/A +i2c-2 unknown i915 gmbus panel N/A +i2c-0 unknown i915 gmbus ssc N/A +i2c-7 unknown SMBus I801 adapter at f040 N/A +i2c-5 unknown i915 gmbus dpd N/A +``` + +Probing the SMBus: + +```bash +$ i2cdetect -r 7 +WARNING! This program can confuse your I2C bus, cause data loss and worse! +I will probe file /dev/i2c-7 using receive byte commands. +I will probe address range 0x03-0x77. +Continue? [Y/n] + 0 1 2 3 4 5 6 7 8 9 a b c d e f +00: -- -- -- -- -- -- -- -- -- -- -- -- -- +10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +30: 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- +50: UU -- UU -- -- -- -- -- -- -- -- -- -- -- -- -- +60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +70: -- -- -- -- -- -- -- -- +``` + +The SPD addresses need to be left-shifted by 1 for `mrc.bin`, i.e., multiplied +by 2. For example, if the addresses read through `i2c-tools` when booted from +vendor firmware are `0x50` and `0x52`, the correct values would be `0xa0` and +`0xa4`. This is because the I2C addresses are 7 bits long. + ## ECC DRAM
When `mrc.bin` has finished executing, ECC is active on the channels
Daniel Maslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32473 )
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Patch Set 2:
:)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32473 )
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/32473/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32473/2//COMMIT_MSG@10 PS2, Line 10: cyrevolt You have to use your real name: https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32473 )
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32473/2/Documentation/northbridge/intel/hasw... File Documentation/northbridge/intel/haswell/mrc.bin.md:
https://review.coreboot.org/#/c/32473/2/Documentation/northbridge/intel/hasw... PS2, Line 68: You can check the correctness of the SMBus and the addresses of the EEPROMs via whitespace
Hello ron minnich, Angel Pons, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32473
to look at the new patch set (#3).
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses
Change-Id: I8bf81637f582373d9bba1d47fe5205d459151f3e Signed-off-by: Daniel Maslowski dan@orangecms.org --- M 3rdparty/blobs M 3rdparty/fsp M Documentation/northbridge/intel/haswell/mrc.bin.md 3 files changed, 79 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32473/3
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32473 )
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Patch Set 3:
(1 comment)
Remove 3rdparty/ changes from the commit.
https://review.coreboot.org/#/c/32473/3/Documentation/northbridge/intel/hasw... File Documentation/northbridge/intel/haswell/mrc.bin.md:
https://review.coreboot.org/#/c/32473/3/Documentation/northbridge/intel/hasw... PS3, Line 106: Only this last paragraph is somewhat haswell mrc.bin -specific, a better place for this documentation is under general mainboard porting. Also, this instruction does not really help to identify the correct order in case of 4 or more DIMM slots on dual-channel boards.
Daniel Maslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32473 )
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Patch Set 3:
(1 comment)
Patch Set 2: Code-Review+1
(1 comment)
Sorry, I didn't understand the concept. I just put something there in order to be able to push because the commit hook didn't let me otherwise. I just want to upstream my patches. :)
https://review.coreboot.org/#/c/32473/2/Documentation/northbridge/intel/hasw... File Documentation/northbridge/intel/haswell/mrc.bin.md:
https://review.coreboot.org/#/c/32473/2/Documentation/northbridge/intel/hasw... PS2, Line 68: You can check the correctness of the SMBus and the addresses of the EEPROMs via
whitespace
Done
Hello ron minnich, Angel Pons, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32473
to look at the new patch set (#4).
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses
Change-Id: I8bf81637f582373d9bba1d47fe5205d459151f3e Signed-off-by: Daniel Maslowski dan@orangecms.org --- M Documentation/northbridge/intel/haswell/mrc.bin.md 1 file changed, 77 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32473/4
Daniel Maslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32473 )
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Patch Set 4:
(1 comment)
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/32473/3/Documentation/northbridge/intel/hasw... File Documentation/northbridge/intel/haswell/mrc.bin.md:
https://review.coreboot.org/#/c/32473/3/Documentation/northbridge/intel/hasw... PS3, Line 106:
Only this last paragraph is somewhat haswell mrc. […]
Yeah that's what I had initially, and when I chatted with Philipp Deppenwiese, he suggested I should add more details on obtaining the information. Do you have suggestions about the order? And where would you put this part then? Maybe here? https://doc.coreboot.org/arch/x86/index.html?highlight=porting#porting-other...
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32473 )
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Patch Set 4: Code-Review+2
There's no mainboard porting guide.
Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32473 )
Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ......................................................................
Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses
Change-Id: I8bf81637f582373d9bba1d47fe5205d459151f3e Signed-off-by: Daniel Maslowski dan@orangecms.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/32473 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M Documentation/northbridge/intel/haswell/mrc.bin.md 1 file changed, 77 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md index 36ab4c4..edfe4b8 100644 --- a/Documentation/northbridge/intel/haswell/mrc.bin.md +++ b/Documentation/northbridge/intel/haswell/mrc.bin.md @@ -27,6 +27,83 @@ Alternatively, place `mrc.bin` anywhere you want, and set `MRC_FILE` to its location when building coreboot.
+## SPD Addresses + +When porting a board from vendor firmware, the SPD addresses can be obtained +through `i2c-tools`, which can be found in many GNU/Linux distributions. A more +[detailed description](https://hannuhartikainen.fi/blog/hacking-ddr3-spd/) of +the procedure and beyond can be found in +[Hannu Hartikainen's blog](https://hannuhartikainen.fi). + +First load the kernel modules: + +```bash +modprobe i2c-dev +modprobe eeprom +``` + +Find the SMBus and the addresses of the DIMM's EEPROMs (example output): +```bash +$ decode-dimms | grep Decoding +Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0050 +Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0052 +``` + +Alternatively, look at the sys filesystem: +```bash +$ ls -l /sys/bus/i2c/drivers/eeprom/ +total 0 +lrwxrwxrwx 1 root root 0 Apr 4 01:46 6-0050 -> ../../../../devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/i2c-6/6-0050/ +lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0050 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0050/ +lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0052 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0052/ +--w------- 1 root root 4096 Apr 4 01:47 bind +lrwxrwxrwx 1 root root 0 Apr 4 01:47 module -> ../../../../module/eeprom/ +--w------- 1 root root 4096 Apr 4 01:46 uevent +--w------- 1 root root 4096 Apr 4 01:47 unbind +``` + +The correct I2C bus is 7 in this case, and the EEPROMs are at `0x50` and `0x52`. +Note that the above values are actually hex values. + +You can check the correctness of the SMBus and the addresses of the EEPROMs via +`i2cdetect`: + +```bash +$ i2cdetect -l +i2c-3 unknown i915 gmbus dpc N/A +i2c-1 unknown i915 gmbus vga N/A +i2c-6 unknown DPDDC-A N/A +i2c-4 unknown i915 gmbus dpb N/A +i2c-2 unknown i915 gmbus panel N/A +i2c-0 unknown i915 gmbus ssc N/A +i2c-7 unknown SMBus I801 adapter at f040 N/A +i2c-5 unknown i915 gmbus dpd N/A +``` + +Probing the SMBus: + +```bash +$ i2cdetect -r 7 +WARNING! This program can confuse your I2C bus, cause data loss and worse! +I will probe file /dev/i2c-7 using receive byte commands. +I will probe address range 0x03-0x77. +Continue? [Y/n] + 0 1 2 3 4 5 6 7 8 9 a b c d e f +00: -- -- -- -- -- -- -- -- -- -- -- -- -- +10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +30: 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- +50: UU -- UU -- -- -- -- -- -- -- -- -- -- -- -- -- +60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +70: -- -- -- -- -- -- -- -- +``` + +The SPD addresses need to be left-shifted by 1 for `mrc.bin`, i.e., multiplied +by 2. For example, if the addresses read through `i2c-tools` when booted from +vendor firmware are `0x50` and `0x52`, the correct values would be `0xa0` and +`0xa4`. This is because the I2C addresses are 7 bits long. + ## ECC DRAM
When `mrc.bin` has finished executing, ECC is active on the channels
-
Angel Pons (Code Review) -
Daniel Maslowski (Code Review)
-
Kyösti Mälkki (Code Review)
-
Patrick Rudolph (Code Review)
-
Philipp Deppenwiese (Code Review)