[XS] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix memory max capacity per processor

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email )

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Change subject: soc/intel/xeon_sp/spr: Fix memory max capacity per processor
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Patch Set 1:

(2 comments)

File src/soc/intel/xeon_sp/spr/romstage.c:

https://review.coreboot.org/c/coreboot/+/75740/comment/1deb31ab_bea27793 :
PS1, Line 277: 	 * Persistent Memory 300 Series mapped as memory) per Socket
I don't understand how to calculate anything from this. What is 3DS?
Is the 6TiB supposed to be the sum of max. DRAM and max. Optane Memory?

https://review.coreboot.org/c/coreboot/+/75740/comment/44fe88ae_3ce82165 :
PS1, Line 279: MiB
I guess this should be `(TiB/MiB)` (note there is already an MiB in
the struct field's name) which is the same value as `MiB` again by
coincidence.