Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49343 )
Change subject: sb/intel: Add CBMC entries in GNVS ......................................................................
sb/intel: Add CBMC entries in GNVS
While unused, this allows use of a common initialisation code for GNVS allocation.
Change-Id: Ie84b5a3e16d3baa12bcd5dadac0b1f7edb323272 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/49343 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/nvs.h M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/nvs.h M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/nvs.h M src/southbridge/intel/ibexpeak/acpi/globalnvs.asl M src/southbridge/intel/ibexpeak/nvs.h 10 files changed, 20 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index ec193c4..9194f3f 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -110,6 +110,7 @@
Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value + CBMC, 32,
/* ChromeOS specific */ Offset (0x100), diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index b75e0ab..949467b 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -100,8 +100,10 @@ /* XHCI */ u8 xhci; u8 rsvd12[65]; + u8 tpiq; /* 0xf5 - trackpad IRQ value */ - u8 rsvd13[10]; /* 0xf6 - rsvd */ + u32 cbmc; + u8 rsvd13[6]; /* 0xfa - rsvd */
/* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 848005d..9b8fd11 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -108,4 +108,5 @@ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable + CBMC, 32, } diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index d2efc5c..b23b85b 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -96,7 +96,9 @@ /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; - u8 rsvd13[14]; + + u32 cbmc; + u8 rsvd13[10]; };
#endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */ diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 5c9e26e..5687eb0 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -110,4 +110,5 @@ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable + CBMC, 32, } diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index e0e6bbd..83dd7e5 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -96,7 +96,9 @@ /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; - u8 rsvd13[14]; + + u32 cbmc; + u8 rsvd13[10]; };
#endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 5c9e26e..5687eb0 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -110,4 +110,5 @@ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable + CBMC, 32, } diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index 48a7d87..96c0a40 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -95,7 +95,9 @@ /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; - u8 rsvd13[14]; + + u32 cbmc; + u8 rsvd13[10]; };
#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl index a650a68..62e3888 100644 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -107,6 +107,7 @@ /* XHCI */ Offset (0xb2), XHCI, 8, + CBMC, 32, }
/* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 799af47..bc18c25 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -98,7 +98,9 @@ u8 rsvd11[6]; /* XHCI */ u8 xhci; - u8 rsvd13[76]; /* 0xf5 - rsvd */ + + u32 cbmc; + u8 rsvd13[72]; /* rsvd */ };
#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */
-
Angel Pons (Code Review)