Change in coreboot[master]: soc/intel/common: Add SOC specific function to get XHCI USB info
Hello Karthikeyan Ramasubramanian,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/34290
to review the following change.
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
soc/intel/common: Add SOC specific function to get XHCI USB info
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required.
BUG=None BRANCH=None TEST=Boot to ChromeOS.
Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/elog.c A src/soc/intel/apollolake/xhci.c M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/elog.c A src/soc/intel/cannonlake/xhci.c M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/elog.c A src/soc/intel/skylake/xhci.c 10 files changed, 126 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34290/1
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4fc16d5..6fd0822 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -44,6 +44,7 @@ smm-y += spi.c smm-y += uart.c smm-y += elog.c +smm-y += xhci.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c @@ -67,6 +68,7 @@ ramstage-y += reset.c ramstage-y += xdci.c ramstage-y += sd.c +ramstage-y += xhci.c
postcar-y += memmap.c postcar-y += mmap_boot.c diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index c138b34..02afb6c 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -25,23 +25,6 @@ #include <soc/smbus.h> #include <stdint.h>
-#define XHCI_USB2_PORT_STATUS_REG 0x480 -#if CONFIG(SOC_INTEL_GLK) -#define XHCI_USB3_PORT_STATUS_REG 0x510 -#define XHCI_USB2_PORT_NUM 9 -#else -#define XHCI_USB3_PORT_STATUS_REG 0x500 -#define XHCI_USB2_PORT_NUM 8 -#endif -#define XHCI_USB3_PORT_NUM 7 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -74,7 +57,7 @@
/* XHCI */ if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS) - pch_xhci_update_wake_event(&usb_info); + pch_xhci_update_wake_event(soc_get_xhci_usb_info());
/* SMBUS Wake */ if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS) diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c new file mode 100644 index 0000000..27adf74 --- /dev/null +++ b/src/soc/intel/apollolake/xhci.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/xhci.h> +#include <stdint.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#if CONFIG(SOC_INTEL_GLK) +#define XHCI_USB3_PORT_STATUS_REG 0x510 +#define XHCI_USB2_PORT_NUM 9 +#else +#define XHCI_USB3_PORT_STATUS_REG 0x500 +#define XHCI_USB2_PORT_NUM 8 +#endif +#define XHCI_USB3_PORT_NUM 7 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a4a8b7..7ff8603 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -56,12 +56,14 @@ ramstage-y += uart.c ramstage-y += vr_config.c ramstage-y += sd.c +ramstage-y += xhci.c
smm-y += elog.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += xhci.c
postcar-y += memmap.c postcar-y += pmutil.c diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 141aa45..0bccdb7 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -24,18 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h>
-#define XHCI_USB2_PORT_STATUS_REG 0x480 -#define XHCI_USB3_PORT_STATUS_REG 0x580 -#define XHCI_USB2_PORT_NUM 14 -#define XHCI_USB3_PORT_NUM 10 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -68,7 +56,7 @@
/* XHCI - "Power Management Event Bus 0" events include XHCI */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - pch_xhci_update_wake_event(&usb_info); + pch_xhci_update_wake_event(soc_get_xhci_usb_info());
/* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) diff --git a/src/soc/intel/cannonlake/xhci.c b/src/soc/intel/cannonlake/xhci.c new file mode 100644 index 0000000..c0ae0f2 --- /dev/null +++ b/src/soc/intel/cannonlake/xhci.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/xhci.h> +#include <stdint.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x580 +#define XHCI_USB2_PORT_NUM 14 +#define XHCI_USB3_PORT_NUM 10 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 86b598f..492c32a 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -46,4 +46,14 @@
void soc_xhci_init(struct device *dev);
+/** + * soc_get_xhci_usb_info() - Get the information about USB2 & USB3 ports. + * + * This function is used to get USB ports and status register offset information + * within a XHCI controller. + * + * Return: USB ports and status register offset info for the SoC. + */ +const struct xhci_usb_info *soc_get_xhci_usb_info(void); + #endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */ diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 20fba29..913a9d9 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -67,6 +67,7 @@ ramstage-y += thermal.c ramstage-y += uart.c ramstage-y += vr_config.c +ramstage-y += xhci.c
smm-y += elog.c smm-y += gpio.c @@ -74,6 +75,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += xhci.c
postcar-y += memmap.c postcar-y += gspi.c diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 359f3e6..83721c8 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -39,18 +39,6 @@ } }
-#define XHCI_USB2_PORT_STATUS_REG 0x480 -#define XHCI_USB3_PORT_STATUS_REG 0x540 -#define XHCI_USB2_PORT_NUM 10 -#define XHCI_USB3_PORT_NUM 6 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - struct pme_status_info { #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; @@ -76,7 +64,7 @@ * USB2/3 ports. */ if ((info->dev == PCH_DEV_XHCI) && - pch_xhci_update_wake_event(&usb_info)) + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) return;
elog_add_event_wake(info->elog_event, 0); diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c new file mode 100644 index 0000000..81c4cc6 --- /dev/null +++ b/src/soc/intel/skylake/xhci.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/xhci.h> +#include <stdint.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x540 +#define XHCI_USB2_PORT_NUM 10 +#define XHCI_USB3_PORT_NUM 6 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +}
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 1: Code-Review+1
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 1: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34290/1/src/soc/intel/apollolake/xh... File src/soc/intel/apollolake/xhci.c:
https://review.coreboot.org/c/coreboot/+/34290/1/src/soc/intel/apollolake/xh... PS1, Line 17: #include <stdint.h> Is this required?
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34290/1/src/soc/intel/apollolake/xh... File src/soc/intel/apollolake/xhci.c:
https://review.coreboot.org/c/coreboot/+/34290/1/src/soc/intel/apollolake/xh... PS1, Line 17: #include <stdint.h>
Is this required?
Seems not required. I will remove it
Hello Paul Fagerburg, Patrick Rudolph, Karthikeyan Ramasubramanian, Paul Fagerburg, Tim Wawrzynczak, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34290
to look at the new patch set (#2).
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
soc/intel/common: Add SOC specific function to get XHCI USB info
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required.
BUG=None BRANCH=None TEST=Boot to ChromeOS.
Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/elog.c A src/soc/intel/apollolake/xhci.c M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/elog.c A src/soc/intel/cannonlake/xhci.c M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/elog.c A src/soc/intel/skylake/xhci.c 10 files changed, 123 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34290/2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34290/1/src/soc/intel/apollolake/xh... File src/soc/intel/apollolake/xhci.c:
https://review.coreboot.org/c/coreboot/+/34290/1/src/soc/intel/apollolake/xh... PS1, Line 17: #include <stdint.h>
Seems not required. […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34290/2/src/soc/intel/skylake/elog.... File src/soc/intel/skylake/elog.c:
https://review.coreboot.org/c/coreboot/+/34290/2/src/soc/intel/skylake/elog.... PS2, Line 115: pch_xhci_update_wake_event(&usb_info) This needs to be updated as well.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34290/2/src/soc/intel/skylake/elog.... File src/soc/intel/skylake/elog.c:
https://review.coreboot.org/c/coreboot/+/34290/2/src/soc/intel/skylake/elog.... PS2, Line 115: pch_xhci_update_wake_event soc_get_xhci_usb_info() ?
Hello Paul Fagerburg, Patrick Rudolph, Karthikeyan Ramasubramanian, Paul Fagerburg, Tim Wawrzynczak, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34290
to look at the new patch set (#3).
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
soc/intel/common: Add SOC specific function to get XHCI USB info
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required.
BUG=None BRANCH=None TEST=Boot to ChromeOS.
Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/elog.c A src/soc/intel/apollolake/xhci.c M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/elog.c A src/soc/intel/cannonlake/xhci.c M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/elog.c A src/soc/intel/skylake/xhci.c 10 files changed, 124 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34290/3
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 3:
(2 comments)
Thanks for catching that.
https://review.coreboot.org/c/coreboot/+/34290/2/src/soc/intel/skylake/elog.... File src/soc/intel/skylake/elog.c:
https://review.coreboot.org/c/coreboot/+/34290/2/src/soc/intel/skylake/elog.... PS2, Line 115: pch_xhci_update_wake_event
soc_get_xhci_usb_info() ?
Done
https://review.coreboot.org/c/coreboot/+/34290/2/src/soc/intel/skylake/elog.... PS2, Line 115: pch_xhci_update_wake_event(&usb_info)
This needs to be updated as well.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 3: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 3: Code-Review+2
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34290 )
Change subject: soc/intel/common: Add SOC specific function to get XHCI USB info ......................................................................
soc/intel/common: Add SOC specific function to get XHCI USB info
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required.
BUG=None BRANCH=None TEST=Boot to ChromeOS.
Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290 Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/elog.c A src/soc/intel/apollolake/xhci.c M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/elog.c A src/soc/intel/cannonlake/xhci.c M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/elog.c A src/soc/intel/skylake/xhci.c 10 files changed, 124 insertions(+), 45 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4fc16d5..6fd0822 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -44,6 +44,7 @@ smm-y += spi.c smm-y += uart.c smm-y += elog.c +smm-y += xhci.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c @@ -67,6 +68,7 @@ ramstage-y += reset.c ramstage-y += xdci.c ramstage-y += sd.c +ramstage-y += xhci.c
postcar-y += memmap.c postcar-y += mmap_boot.c diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index c138b34..02afb6c 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -25,23 +25,6 @@ #include <soc/smbus.h> #include <stdint.h>
-#define XHCI_USB2_PORT_STATUS_REG 0x480 -#if CONFIG(SOC_INTEL_GLK) -#define XHCI_USB3_PORT_STATUS_REG 0x510 -#define XHCI_USB2_PORT_NUM 9 -#else -#define XHCI_USB3_PORT_STATUS_REG 0x500 -#define XHCI_USB2_PORT_NUM 8 -#endif -#define XHCI_USB3_PORT_NUM 7 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -74,7 +57,7 @@
/* XHCI */ if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS) - pch_xhci_update_wake_event(&usb_info); + pch_xhci_update_wake_event(soc_get_xhci_usb_info());
/* SMBUS Wake */ if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS) diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c new file mode 100644 index 0000000..1316107 --- /dev/null +++ b/src/soc/intel/apollolake/xhci.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/xhci.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#if CONFIG(SOC_INTEL_GLK) +#define XHCI_USB3_PORT_STATUS_REG 0x510 +#define XHCI_USB2_PORT_NUM 9 +#else +#define XHCI_USB3_PORT_STATUS_REG 0x500 +#define XHCI_USB2_PORT_NUM 8 +#endif +#define XHCI_USB3_PORT_NUM 7 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a4a8b7..7ff8603 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -56,12 +56,14 @@ ramstage-y += uart.c ramstage-y += vr_config.c ramstage-y += sd.c +ramstage-y += xhci.c
smm-y += elog.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += xhci.c
postcar-y += memmap.c postcar-y += pmutil.c diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 141aa45..0bccdb7 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -24,18 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h>
-#define XHCI_USB2_PORT_STATUS_REG 0x480 -#define XHCI_USB3_PORT_STATUS_REG 0x580 -#define XHCI_USB2_PORT_NUM 14 -#define XHCI_USB3_PORT_NUM 10 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -68,7 +56,7 @@
/* XHCI - "Power Management Event Bus 0" events include XHCI */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - pch_xhci_update_wake_event(&usb_info); + pch_xhci_update_wake_event(soc_get_xhci_usb_info());
/* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) diff --git a/src/soc/intel/cannonlake/xhci.c b/src/soc/intel/cannonlake/xhci.c new file mode 100644 index 0000000..2741883 --- /dev/null +++ b/src/soc/intel/cannonlake/xhci.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/xhci.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x580 +#define XHCI_USB2_PORT_NUM 14 +#define XHCI_USB3_PORT_NUM 10 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 86b598f..492c32a 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -46,4 +46,14 @@
void soc_xhci_init(struct device *dev);
+/** + * soc_get_xhci_usb_info() - Get the information about USB2 & USB3 ports. + * + * This function is used to get USB ports and status register offset information + * within a XHCI controller. + * + * Return: USB ports and status register offset info for the SoC. + */ +const struct xhci_usb_info *soc_get_xhci_usb_info(void); + #endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */ diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 20fba29..913a9d9 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -67,6 +67,7 @@ ramstage-y += thermal.c ramstage-y += uart.c ramstage-y += vr_config.c +ramstage-y += xhci.c
smm-y += elog.c smm-y += gpio.c @@ -74,6 +75,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += xhci.c
postcar-y += memmap.c postcar-y += gspi.c diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 359f3e6..47d6137 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -39,18 +39,6 @@ } }
-#define XHCI_USB2_PORT_STATUS_REG 0x480 -#define XHCI_USB3_PORT_STATUS_REG 0x540 -#define XHCI_USB2_PORT_NUM 10 -#define XHCI_USB3_PORT_NUM 6 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - struct pme_status_info { #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; @@ -76,7 +64,7 @@ * USB2/3 ports. */ if ((info->dev == PCH_DEV_XHCI) && - pch_xhci_update_wake_event(&usb_info)) + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) return;
elog_add_event_wake(info->elog_event, 0); @@ -124,7 +112,7 @@ * PME_STS_BIT in controller register. */ if (!dev_found) - dev_found = pch_xhci_update_wake_event(&usb_info); + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info());
if (!dev_found) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c new file mode 100644 index 0000000..bca3b86 --- /dev/null +++ b/src/soc/intel/skylake/xhci.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/xhci.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x540 +#define XHCI_USB2_PORT_NUM 10 +#define XHCI_USB3_PORT_NUM 6 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +}
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