Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports

[Benjamin Doron (Code Review)]

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39538

to look at the new patch set (#11).

Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
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soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports

Port commit 84b4882b (soc/intel/tigerlake: Configure L1Substates for
PCH Root ports), CB:39412) to Skylake. Exposes PcieRpAspm and
PcieRpL1Substates to devicetree to allow boards to set these options.

get_{aspm,l1_substate}_control() ensure that the right UPD value is set in
fsp_params.

Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron 
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 56 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/11