Change in coreboot[master]: tgl/usb: disable TBT if hardware is not USB4

[Nick Vaccaro (Code Review)]

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45945 )

Change subject: tgl/usb: disable TBT if hardware is not USB4
......................................................................

tgl/usb: disable TBT if hardware is not USB4

TBT being enabled in FSP without USB4 hardware causes an issue
powering off in depthcharge.  Disable TBT for FSP if USB hardware
is not USB4.

BUG=b:167983038
TEST=none

Change-Id: Icbe743f917bf0a6899fe4587db8a2ddd60715c88
Signed-off-by: Nick Vaccaro 
---
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/fsp_params.c
A src/soc/intel/tigerlake/include/soc/mainboard_support.h
A src/soc/intel/tigerlake/mainboard_weak_support.c
M src/soc/intel/tigerlake/romstage/fsp_params.c
5 files changed, 29 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45945/1

diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc
index c4f71c7..4a68e68 100644
--- a/src/soc/intel/tigerlake/Makefile.inc
+++ b/src/soc/intel/tigerlake/Makefile.inc
@@ -24,8 +24,9 @@
 bootblock-y += p2sb.c

romstage-y += espi.c
-romstage-y += meminit.c
 romstage-y += gpio.c
+ramstage-y += mainboard_weak_support.c
+romstage-y += meminit.c
 romstage-y += reset.c

ramstage-y += acpi.c
@@ -37,6 +38,7 @@
 ramstage-y += fsp_params.c
 ramstage-y += gpio.c
 ramstage-y += lockdown.c
+ramstage-y += mainboard_weak_support.c
 ramstage-y += p2sb.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 38f444b..551aef11 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -16,6 +16,7 @@
 #include <security/vboot/vboot_common.h>
 #include <soc/gpio_soc_defs.h>
 #include <soc/intel/common/vbt.h>
+#include <soc/mainboard_support.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
@@ -310,10 +311,13 @@
    /* USB4/TBT */
    for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {
    	dev = pcidev_on_root(SA_DEV_SLOT_TBT, i);
-		if (dev)
+		if (is_dev_enabled(dev) && mainboard_supports_usb4()) {
+			printk(BIOS_INFO,
+			       "ITbtPcieRootPortEn%d is enabled\n", i);
    		params->ITbtPcieRootPortEn[i] = dev->enabled;
-		else
+		} else {
    		params->ITbtPcieRootPortEn[i] = 0;
+		}
    }

/* PCH FIVR settings override */
diff --git a/src/soc/intel/tigerlake/include/soc/mainboard_support.h b/src/soc/intel/tigerlake/include/soc/mainboard_support.h
new file mode 100644
index 0000000..a43fa33
--- /dev/null
+++ b/src/soc/intel/tigerlake/include/soc/mainboard_support.h
@@ -0,0 +1,10 @@
+#ifndef _SOC_MAINBOARD_SUPPORT_H_
+#define _SOC_MAINBOARD_SUPPORT_H_
+
+#include <fsp/util.h>
+
+bool mainboard_supports_usb4(void);
+
+#endif
+
+
diff --git a/src/soc/intel/tigerlake/mainboard_weak_support.c b/src/soc/intel/tigerlake/mainboard_weak_support.c
new file mode 100644
index 0000000..ecf22c34
--- /dev/null
+++ b/src/soc/intel/tigerlake/mainboard_weak_support.c
@@ -0,0 +1,9 @@
+#include <console/console.h>
+#include <soc/mainboard_support.h>
+
+bool __weak mainboard_supports_usb4(void)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+	return false;
+}
+
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index dc9caee..f2b9649 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -9,6 +9,7 @@
 #include <intelblocks/mp_init.h>
 #include <soc/gpio_soc_defs.h>
 #include <soc/iomap.h>
+#include <soc/mainboard_support.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>

[Nick Vaccaro (Code Review)]

Nick Vaccaro has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45945 )

Change subject: tgl/usb: disable TBT if hardware is not USB4
......................................................................

Abandoned

change-id changed, this should not be a new CL, changed back to https://review.coreboot.org/c/coreboot/+/45946