Change in coreboot[master]: TEST-ONLY: soc/mediatek/mt8192: workaround for samsung dram(type: 0)

[Xi Chen (Code Review)]

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47987 )

Change subject: TEST-ONLY: soc/mediatek/mt8192: workaround for samsung dram(type: 0)
......................................................................

TEST-ONLY: soc/mediatek/mt8192: workaround for samsung dram(type: 0)

Signed-off-by: Xi Chen 
Change-Id: I232e325af5e8ce77a1289e2001900850fadcec21
---
M src/mainboard/google/asurada/sdram_configs.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/47987/1

diff --git a/src/mainboard/google/asurada/sdram_configs.c b/src/mainboard/google/asurada/sdram_configs.c
index acefada..6fbc376 100644
--- a/src/mainboard/google/asurada/sdram_configs.c
+++ b/src/mainboard/google/asurada/sdram_configs.c
@@ -18,10 +18,10 @@
 {
    uint32_t ramcode = ram_code();

-	if (ramcode >= ARRAY_SIZE(sdram_configs) ||
-	    cbfs_boot_load_file(sdram_configs[ramcode], &params, sizeof(params),
-				CBFS_TYPE_STRUCT) != sizeof(params))
+	if (ramcode >= ARRAY_SIZE(sdram_configs))
    	die("Cannot load SDRAM parameter file for RAM code: %#x", ramcode);

+	// patch for samsung: dram type: 0
+	params.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2;
    return &params;
 }

[Xi Chen (Code Review)]

Xi Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47987 )

Change subject: TEST-ONLY: soc/mediatek/mt8192: workaround for samsung dram(type: 0)
......................................................................

Abandoned