Change in coreboot[master]: mb/google/cherry: Pre-initialize PCIe at the bootblock stage

[Paul Fagerburg (Code Review)]

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62359 )

Change subject: mb/google/cherry: Pre-initialize PCIe at the bootblock stage
......................................................................

mb/google/cherry: Pre-initialize PCIe at the bootblock stage

Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be
delayed 100ms (TPVPERL) for the power and clock to become stable.

Instead of asserting PERST# right before PCIe initialization and waiting
for 100ms, which is currently the only function of 'mtk_pcie_pre_init',
so that the extra 100ms delay in ramstage is avoided.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang 
Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Menzel 
Reviewed-by: Yu-Ping Wu 
---
M src/mainboard/google/cherry/bootblock.c
M src/soc/mediatek/mt8195/Makefile.inc
2 files changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c
index c506caf..c811c4e 100644
--- a/src/mainboard/google/cherry/bootblock.c
+++ b/src/mainboard/google/cherry/bootblock.c
@@ -5,6 +5,7 @@
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <soc/i2c.h>
+#include <soc/pcie.h>
 #include <soc/spi.h>

#include "gpio.h"
@@ -43,6 +44,13 @@

void bootblock_mainboard_init(void)
 {
+	/*
+	 * Initialize PCIe pinmux and assert PERST# early to reduce
+	 * the impact of 100ms delay.
+	 */
+	if (CONFIG(PCI))
+		mtk_pcie_pre_init();
+
    mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
    mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
    nor_set_gpio_pinmux();
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index b83fc32..0a305d9 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -9,6 +9,7 @@
 bootblock-y += ../common/i2c.c i2c.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-y += ../common/tracker.c ../common/tracker_v2.c
+bootblock-$(CONFIG_PCI) += pcie.c
 bootblock-y += ../common/pll.c pll.c
 bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 bootblock-y += ../common/timer.c timer.c