Change in coreboot[master]: soc/mediatek/mt8186: Adjust usage of SRAM L2C

[Rex-BC Chen (Code Review)]

Attention is currently required from: Hung-Te Lin, Paul Menzel.
Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60316 )

Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C
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Patch Set 5:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60316/comment/32fc43f2_bee70964 
PS4, Line 8:
> Please describe the problem at hand.

Done

https://review.coreboot.org/c/coreboot/+/60316/comment/bf4995a9_78eb7150 
PS4, Line 9: However the BootROM
           : has configured only half of L2/L3 cache as SRAM.
> Is that a bug? Can the BootROM be fixed?

No, it's not a bug.
BootRom configures this setting to use this memory as half for data cache and half for SRAM.
It's almost impossible to change this setting from BootRom because it's not unchangeable when the SoCs are taped out.