Change in coreboot[master]: mainboard/compulab: enable SuperIO UART

[Hal Martin (Code Review)]

Hal Martin has uploaded this change for review. ( https://review.coreboot.org/22737

Change subject: mainboard/compulab: enable SuperIO UART
......................................................................

mainboard/compulab: enable SuperIO UART

Enable the UART via SMSC SIO1007 SuperIO,
this allows you to see boot messages from
coreboot over the integrated RS-232 port
(requires use of included dongle).

Also changed devicetree to use the correct CPU socket.

Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567
Signed-off-by: Hal Martin 
---
M src/mainboard/compulab/intense_pc/Kconfig
M src/mainboard/compulab/intense_pc/devicetree.cb
M src/mainboard/compulab/intense_pc/romstage.c
3 files changed, 60 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/22737/1

diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig
index 283d63a..6375495 100644
--- a/src/mainboard/compulab/intense_pc/Kconfig
+++ b/src/mainboard/compulab/intense_pc/Kconfig
@@ -14,6 +14,7 @@
    select SOUTHBRIDGE_INTEL_C216
    select SYSTEM_TYPE_LAPTOP
    select USE_NATIVE_RAMINIT
+	select SUPERIO_SMSC_SIO1007

config HAVE_IFD_BIN
    bool
diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb
index 8b1deb3..6d01892 100644
--- a/src/mainboard/compulab/intense_pc/devicetree.cb
+++ b/src/mainboard/compulab/intense_pc/devicetree.cb
@@ -28,7 +28,7 @@
    register "gpu_panel_power_up_delay" = "0"
    register "gpu_pch_backlight" = "0x00000000"
    device cpu_cluster 0x0 on
-		chip cpu/intel/socket_rPGA989
+		chip cpu/intel/socket_FCBGA1023
    		device lapic 0x0 on
    		end
    	end
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c
index 8ef3f3e..1df8495 100644
--- a/src/mainboard/compulab/intense_pc/romstage.c
+++ b/src/mainboard/compulab/intense_pc/romstage.c
@@ -17,7 +17,9 @@
 #include <lib.h>
 #include <arch/io.h>
 #include "northbridge/intel/sandybridge/raminit_native.h"
+#include <superio/smsc/sio1007/chip.h>

+/*
 void pch_enable_lpc(void)
 {
    pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
@@ -27,6 +29,33 @@
    pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
    pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
    pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
+}
+*/
+
+#define SIO_PORT 0x164e
+
+void pch_enable_lpc(void)
+{
+	device_t dev = PCH_LPC_DEV;
+
+	/* Set COM1/COM2 decode range */
+	pci_write_config16(dev, LPC_IO_DEC, 0x0010);
+
+	/* Enable SuperIO + PS/2 Keyboard/Mouse */
+	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
+	pci_write_config16(dev, LPC_EN, lpc_config);
+
+	/* Map 256 bytes at 0x1600 to the LPC bus. */
+	pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601);
+
+	/* Map a range for the runtime_port registers to the LPC bus. */
+	pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
+
+	/* Enable COM1 */
+	if (sio1007_enable_uart_at(SIO_PORT)) {
+		pci_write_config16(dev, LPC_EN,
+				   lpc_config | COMA_LPC_EN);
+	}
 }

void rcba_config(void)
@@ -59,6 +88,35 @@

void mainboard_config_superio(void)
 {
+	const u16 port = SIO_PORT;
+	const u16 runtime_port = 0x180;
+
+	/* Turn on configuration mode. */
+	outb(0x55, port);
+
+	/* Set the GPIO direction, polarity, and type. */
+	sio1007_setreg(port, 0x31, 1 << 0, 1 << 0);
+	sio1007_setreg(port, 0x32, 0 << 0, 1 << 0);
+	sio1007_setreg(port, 0x33, 0 << 0, 1 << 0);
+
+	/* Set the base address for the runtime register block. */
+	sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff);
+	sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff);
+
+	/* Turn on address decoding for it. */
+	sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1);
+
+	/* Set the value of GPIO 10 by changing GP1, bit 0. */
+	u8 byte;
+	byte = inb(runtime_port + 0xc);
+	byte |= (1 << 0);
+	outb(byte, runtime_port + 0xc);
+
+	/* Turn off address decoding for it. */ 
+	sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1);
+
+	/* Turn off configuration mode. */
+	outb(0xaa, port);
 }

void mainboard_get_spd(spd_raw_data *spd, bool id_only)