Change in coreboot[master]: soc/intel/broadwell: Add option to disable PCIe AER capability

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25326

Change subject: soc/intel/broadwell: Add option to disable PCIe AER capability
......................................................................

soc/intel/broadwell: Add option to disable PCIe AER capability

The Advanced Error Reporting capability was hardcoded in the PCIe
extended capability list, but it might not always be possible.

The Librem 13v1 does not seem to have working AER and this option
was needed and tested on the Librem 13v1. Without it, the linux
console gets spammed with AER errrors.

Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe
Signed-off-by: Youness Alaoui 
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/pcie.c
2 files changed, 10 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25326/1

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index cfab489..5d8d602 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -47,6 +47,10 @@
    bool
    default y

+config PCIEXP_AER
+	bool
+	default y
+
 config PCIEXP_COMMON_CLOCK
    bool
    default y
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index cf25749..53a1eac 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -554,8 +554,12 @@
    pci_update_config8(dev, 0xf5, 0x0f, 0);

/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
-	pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
-		(1 << 29) | 0x10001);
+	if (IS_ENABLED(CONFIG_PCIEXP_AER))
+		pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
+			(1 << 29) | 0x10001);
+	else
+		pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
+			(1 << 29));

/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
    if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE))