[S] Change in coreboot[main]: soc/amd/cezanne: add option to disable I2S master clock output of FCH

[Anand Vaikar (Code Review)]

Attention is currently required from: Ana Carolina Cabral, Anand Vaikar, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nick Kochlowski.

Hello Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85865?usp=email

to look at the new patch set (#4).

The following approvals got outdated and were removed:
Code-Review+1 by Ana Carolina Cabral, Verified+1 by build bot (Jenkins)

Change subject: soc/amd/cezanne: add option to disable I2S master clock output of FCH
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soc/amd/cezanne: add option to disable I2S master clock output of FCH

Add a devicetree option to disable the 48MHz clock output of the FCH
when an I2S audio coded uses a separate oscillator for its 48 MHz
master clock instead of the FCH clock output. This code was ported
from the Picasso code base.

Change-Id: I0c1bee121f528d28d591dace260507b345dfec26
Signed-off-by: Anand Vaikar 
---
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
2 files changed, 12 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85865/4