Change in coreboot[master]: cpu/intel/common/fsb.c: Add Broadwell CPUID models

[Angel Pons (Code Review)]

Attention is currently required from: Matt DeVillier, Angel Pons, Arthur Heymans.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Matt DeVillier, Arthur Heymans, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/49939

to look at the new patch set (#2).

Change subject: cpu/intel/common/fsb.c: Add Broadwell CPUID models
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cpu/intel/common/fsb.c: Add Broadwell CPUID models

Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for
both the traditional and ULT variants of Broadwell, because the CPU
driver for Haswell already contains CPUIDs for both Broadwell types.

Without this patch, Broadwell CPUs would hang when trying to print the
first console log message, but only if flashconsole was not enabled.

This was missed in commit f542b7bcef (cpu/intel/haswell: Add Broadwell
CPUIDs and microcode) and went unnoticed until now because the tests
were done with flashconsole enabled, which somehow boots properly even
though the console time tracking would not work (depends on TSC).

Tested on out-of-tree Acer E5-573, fixes booting without flashconsole.

Change-Id: I78a1696771d4d6d2138ec432dc0d8e030f14293b
Signed-off-by: Angel Pons 
---
M src/cpu/intel/common/fsb.c
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/49939/2