Change in coreboot[master]: nb/intel/x4x/raminit: Add write leveling

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

https://review.coreboot.org/19878

to look at the new patch set (#5).

Change subject: nb/intel/x4x/raminit: Add write leveling
......................................................................

nb/intel/x4x/raminit: Add write leveling

DDR3 adapter a fly-by topology which allows for better signal
integrity but at the same time requires additional calibration.
This is done by settings the targeted rank in write leveling mode
while disabling output buffer on the other ranks.

DQS DLL settings are sampled until an edge is found over the DQ
probe. The results are stored in the sysinfo struct for later S3
support.

Change-Id: Ibfbaa235bc4eb08e9345321b851e880390a624e8
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/Makefile.inc
A src/northbridge/intel/x4x/dq_dqs_dll.c
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/intel/x4x/raminit_tables.c
M src/northbridge/intel/x4x/x4x.h
5 files changed, 467 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/19878/5