[S] Change in coreboot[main]: arch/riscv/pmp: Add print macro

[Maximilian Brune (Code Review)]

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83056?usp=email )

Change subject: arch/riscv/pmp: Add print macro
......................................................................

arch/riscv/pmp: Add print macro

This adds a printk macro in the PMP code to avoid all harts writing onto
the serial which causes crappy/broken output.

Signed-off-by: Maximilian Brune 
Change-Id: Icaded168bd7302ad1ea29bebb7900810ebeff92d
---
M src/arch/riscv/pmp.c
1 file changed, 14 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/83056/1

diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c
index b643441..0d1901f 100644
--- a/src/arch/riscv/pmp.c
+++ b/src/arch/riscv/pmp.c
@@ -6,6 +6,13 @@
 #include <console/console.h>
 #include <commonlib/helpers.h>

+/* PMP stuff is often execute on multiple harts, which screws up the debug output. Therefore define a small wrapper which makes sure we only print on one hart. All PMP registers are usually set the same on all harts, so it shouldn't matter much.
+ */
+#define PMP_PRINTK(level, fmt, ...) { \
+	if (read_csr(mhartid) == CONFIG_RISCV_WORKING_HARTID) \
+		printk(level, fmt, __VA_ARGS__); \
+	}
+
 #define GRANULE		(1 << PMP_SHIFT)

/*
@@ -107,19 +114,19 @@
    	new = (old & ~((uintptr_t)0xff << shift))
    		| ((cfg & 0xff) << shift);
    	write_csr(pmpcfg0, new);
-		printk(BIOS_INFO, "%s(%d, %lx) = %lx\n", __func__, idx, cfg, read_csr(pmpcfg0));
+		PMP_PRINTK(BIOS_INFO, "%s(%d, %lx) = %lx\n", __func__, idx, cfg, read_csr(pmpcfg0));
    	break;
    case 1:
    	old = read_csr(pmpcfg2);
    	new = (old & ~((uintptr_t)0xff << shift))
    		| ((cfg & 0xff) << shift);
    	write_csr(pmpcfg2, new);
-		printk(BIOS_INFO, "%s(%d, %lx) = %lx\n", __func__, idx, cfg, read_csr(pmpcfg2));
+		PMP_PRINTK(BIOS_INFO, "%s(%d, %lx) = %lx\n", __func__, idx, cfg, read_csr(pmpcfg2));
    	break;
    }
 #endif
    if (read_pmpcfg(idx) != cfg) {
-		printk(BIOS_WARNING, "%s: PMPcfg%d: Wrote %lx, read %lx\n", __func__, idx, cfg, read_pmpcfg(idx));
+		PMP_PRINTK(BIOS_WARNING, "%s: PMPcfg%d: Wrote %lx, read %lx\n", __func__, idx, cfg, read_pmpcfg(idx));
    	die("PMPcfg write failed");
    }
 }
@@ -218,10 +225,11 @@
    	break;
    }

-	printk(BIOS_INFO, "%s(%d, %lx) = %lx\n", __func__, idx, val, read_pmpaddr(idx));
+		PMP_PRINTK(BIOS_INFO, "%s(%d, %lx) = %lx\n", __func__, idx, val, read_pmpaddr(idx));
    /* The PMP is not required to return what we wrote. On some SoC, many bits are cleared. */
    if (read_pmpaddr(idx) != val) {
-		printk(BIOS_WARNING, "%s: PMPaddr%d: Wrote %lx, read %lx\n", __func__,
+		if (read_csr(mhartid) == CONFIG_RISCV_WORKING_HARTID)
+			PMP_PRINTK(BIOS_WARNING, "%s: PMPaddr%d: Wrote %lx, read %lx\n", __func__,
    			idx, val, read_pmpaddr(idx));
    }
 }
@@ -263,7 +271,7 @@
 #if __riscv_xlen == 32
    /* verify that base + size fits in 34 bits */
    if ((base + size - 1) >> 34) {
-		printk(BIOS_EMERG, "%s: base (%llx) + size (%llx) - 1 is more than 34 bits\n",
+		PMP_PRINTK(BIOS_EMERG, "%s: base (%llx) + size (%llx) - 1 is more than 34 bits\n",
    			__func__, base, size);
    	return 1;
    }