Change in coreboot[master]: soc/intel/tigerlake: Add known GPIO virtual wire indexes

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52589 )

Change subject: soc/intel/tigerlake: Add known GPIO virtual wire indexes
......................................................................

soc/intel/tigerlake: Add known GPIO virtual wire indexes

Change-Id: Icc4581e61ee904cbd998738962d360a58d24bc35
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/tigerlake/gpio.c
1 file changed, 22 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/52589/1

diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c
index f8d4abc..3e45413 100644
--- a/src/soc/intel/tigerlake/gpio.c
+++ b/src/soc/intel/tigerlake/gpio.c
@@ -37,15 +37,23 @@
  * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
  */
 static const struct pad_group tgl_community0_groups[] = {
-	INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0),			/* GPP_B */
-	INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32),			/* GPP_T */
-	INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 64),			/* GPP_A */
+	INTEL_GPP_BASE_VW(GPP_B0, GPP_B0, GPP_B7, 0, 0x13),	/* GPP_B */
+	INTEL_GPP_BASE_VW(GPP_B0, GPP_B15, GPP_B16, 8, 0x14),
+	INTEL_GPP_BASE_VW(GPP_B0, GPP_B16, GPP_B23, 16, 0x15),
+	INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32),		/* GPP_T */
+	INTEL_GPP_BASE_VW(GPP_B0, GPP_A0, GPP_A7, 64, 0x10),	/* GPP_A */
+	INTEL_GPP_BASE_VW(GPP_B0, GPP_A8, GPP_A15, 72, 0x11),
+	INTEL_GPP_BASE_VW(GPP_B0, GPP_A16, GPP_A23, 80, 0x12),
 };

static const struct pad_group tgl_community1_groups[] = {
    INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96),			/* GPP_S */
-	INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128),			/* GPP_H */
-	INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160),	/* GPP_D */
+	INTEL_GPP_BASE_VW(GPP_S0, GPP_H0, GPP_H7, 128, 0x12),		/* GPP_H */
+	INTEL_GPP_BASE_VW(GPP_S0, GPP_H8, GPP_H15, 136, 0x13),
+	INTEL_GPP_BASE_VW(GPP_S0, GPP_H16, GPP_H23, 144, 0x14),
+	INTEL_GPP_BASE_VW(GPP_S0, GPP_D0, GPP_D7, 160, 0x10),		/* GPP_D */
+	INTEL_GPP_BASE_VW(GPP_S0, GPP_D8, GPP_D15, 168, 0x11),
+	INTEL_GPP_BASE_VW(GPP_S0, GPP_D16, GPP_GSPI2_CLK_LOOPBK, 176, 0x12),
    INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192),	/* GPP_U */
    INTEL_GPP_BASE(GPP_S0, CNV_BTEN, vI2S2_RXD, 224),		/* GPP_VGPIO */
 };
@@ -56,10 +64,16 @@
 };

static const struct pad_group tgl_community4_groups[] = {
-	INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256),			/* GPP_C */
-	INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288),		/* GPP_F */
+	INTEL_GPP_BASE_VW(GPP_C0, GPP_C0, GPP_C7, 256, 0x13),		/* GPP_C */
+	INTEL_GPP_BASE_VW(GPP_C0, GPP_C8, GPP_C15, 264, 0x14),
+	INTEL_GPP_BASE_VW(GPP_C0, GPP_C16, GPP_C23, 272, 0x15),
+	INTEL_GPP_BASE_VW(GPP_C0, GPP_F0, GPP_F7, 288, 0x10),		/* GPP_F */
+	INTEL_GPP_BASE_VW(GPP_C0, GPP_F8, GPP_F15, 296, 0x11),
+	INTEL_GPP_BASE_VW(GPP_C0, GPP_F16, GPP_F_CLK_LOOPBK, 304, 0x12),
    INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB),			/* GPP_HVCMOS */
-	INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320),		/* GPP_E */
+	INTEL_GPP_BASE_VW(GPP_C0, GPP_E0, GPP_E7, 320, 0x16),		/* GPP_E */
+	INTEL_GPP_BASE_VW(GPP_C0, GPP_E8, GPP_E15, 328, 0x17),
+	INTEL_GPP_BASE_VW(GPP_C0, GPP_E16, GPP_E_CLK_LOOPBK, 336, 0x18),
    INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE),			/* GPP_JTAG */
 };