Change in coreboot[master]: soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust

[chris wang (Code Review)]

Attention is currently required from: Kevin Chiu, Felix Held.
chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50240 )

Change subject: soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust
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Patch Set 13:

(3 comments)

File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/50240/comment/cf90e072_233ad5cb 
PS7, Line 75: #define USB3_PORT_COUNT 4
> Yes, check with the design guide, the USB3 phy setting should only apply to controller 0. […]

Done

File src/soc/amd/picasso/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/50240/comment/63312e1e_0a0ac299 
PS4, Line 131: memcpy(&scfg->usb_3_port0_phy_tune, &cfg->usb3_phy_tune_params[0],
             : 			sizeof(scfg->usb_3_port0_phy_tune[0]));
> yes, The default value was given in both trembyle and dalboz devtree. […]

Done

File src/vendorcode/amd/fsp/picasso/FspsUpd.h:

https://review.coreboot.org/c/coreboot/+/50240/comment/cb75af72_c23f2363 
PS7, Line 61: 	/** Offset 0x0143**/	uint8_t                     usb_3_port3_phy_tune[2];
> those port should belong to controller 0 and in our Picasso-PI or Pollock-PI. […]

Done