Change in coreboot[master]: soc/intel/alderlake: Add lp5_ccc_config to the board memory configura...

[Subrata Banik (Code Review)]

Subrata Banik has uploaded a new patch set (#5) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/47436 )

Change subject: soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration
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soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration

TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override.

Signed-off-by: Sridhar Siricilla 
Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a
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M src/soc/intel/alderlake/include/soc/meminit.h
M src/soc/intel/alderlake/meminit.c
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47436/5