Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36525 )
Change subject: intel/i440bx: Switch to UDELAY_TSC ......................................................................
intel/i440bx: Switch to UDELAY_TSC
Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/slot_1/Kconfig M src/northbridge/intel/i440bx/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/36525/1
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 3d0522a..10001bd 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -24,7 +24,8 @@ select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX select NO_SMM - select NO_MONOTONIC_TIMER + select UDELAY_TSC + select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE
config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 45cdd9c..df1e365 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,7 +17,6 @@ bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select UDELAY_IO
config SDRAMPWR_4DIMM bool
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36525 )
Change subject: intel/i440bx: Switch to UDELAY_TSC ......................................................................
Patch Set 1: Code-Review+1
Should this be tested?
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36525
to look at the new patch set (#2).
Change subject: intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER ......................................................................
intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER
Note that due to UNKNOWN_TSC_RATE, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the cpu.
Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/slot_1/Kconfig M src/northbridge/intel/i440bx/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/36525/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36525 )
Change subject: intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER ......................................................................
Patch Set 4:
Patch Set 1: Code-Review+1
Should this be tested?
Well.. yes. And improved with tsc_freq_mhz() implementation like message says.
There are 'rdtsc' calls in bootblock and timestamps already.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36525 )
Change subject: intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER ......................................................................
Patch Set 5:
Arthur, see comment about rdtsc beind used before, I think this is safe.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36525 )
Change subject: intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER ......................................................................
Patch Set 5: Code-Review+2
Patch Set 5:
Arthur, see comment about rdtsc beind used before, I think this is safe.
I vaguely remember something about rdtsc being too imprecise for udelay. It's unlikely this platform requires high precision in that regard.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36525 )
Change subject: intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER ......................................................................
Patch Set 5:
Patch Set 5: Code-Review+2
Patch Set 5:
Arthur, see comment about rdtsc beind used before, I think this is safe.
I vaguely remember something about rdtsc being too imprecise for udelay. It's unlikely this platform requires high precision in that regard.
Well.. UDELAY_IO implements udelay() with inb(0x80). My recent experience was each inb took 80us in p4-netburst/cache_as_ram.S.
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36525 )
Change subject: intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER ......................................................................
intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER
Note that due to UNKNOWN_TSC_RATE, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the cpu.
Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36525 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/slot_1/Kconfig M src/northbridge/intel/i440bx/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 3d0522a..10001bd 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -24,7 +24,8 @@ select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX select NO_SMM - select NO_MONOTONIC_TIMER + select UDELAY_TSC + select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE
config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 45cdd9c..df1e365 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,7 +17,6 @@ bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select UDELAY_IO
config SDRAMPWR_4DIMM bool
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)