Attention is currently required from: Nicholas Sudsgaard.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email )
Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake) ......................................................................
Patch Set 27:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80343/comment/15e4b8ba_0a68b740 : PS27, Line 34: - Power button LED Looks like this LED is connected to GPIO `GP10` on the Super I/O. But the input/output control register is only accessible through "Simple I/O" (`io 0x62 = 0x0a00`).
You could try to toggle the GPIO output level through the control register using Simple I/O (as long as the base address has been programmed and LPC forwarding has been enabled), but I'm not even sure which register this would be. You could try comparing the Simple I/O address space between vendor firmware and coreboot by reading several bytes starting from the Simple I/O base address.
Ooooor you could just toggle the polarity of GP10: `irq 0xb0 = 0x01` in the devicetree (if that works, you can try to do it earlier in C code).
Also, if you want to make the power LED blink, you probably need to set bit 0 in GPIO LDN, offset 0xf9. https://i.imgur.com/UIWO3G6.png is a table from the IT8625E datasheet (which is close enough to your chip, at least in this regard), you could even change the blinking rate if you wish. This should work no matter if the polarity is inverted or not.
File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80343/comment/de24d845_2cc5b738 : PS27, Line 12: register "PcieRpClkReqSupport[0]" = "true" : register "PcieRpClkReqNumber[0]" = "2" : register "PcieRpClkSrcNumber[0]" = "0" I think the FSP UPDs exist, but they may not be exposed as devicetree settings.
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Angel Pons (Code Review)