Marc Jones has posted comments on this change. ( https://review.coreboot.org/19722 )
Change subject: soc: Add AMD Stoney Ridge southbridge code ......................................................................
Patch Set 4:
created the following issues to track problems found in review: Kahlee: coreboot - stoneyridge - check uart index bounds 62201567 Kahlee: coreboot - stoneyridge - use device macros 62200746 Kahlee: coreboot -stoneyridge - fix lpc.c 62200877 Kahlee: coreboot -- stoneyridge - fix and find the correct location for amd_pci_int_types.h 62200834 Kahlee: coreboot - stoneyridge - find the correct location for amd_pci_int_defs.h 62200907 Kahlee: coreboot -stoneyridge - fix guarded code 62200858 Kahlee: coreboot - stoneyridge - clean up hudson.c 62200891 Kahlee: coreboot - stoneyridge - rename hudson.c and hudson.h 62200157 Kahlee: coreboot - stoneyridge - cleanup sd.c 62200312 Kahlee: coreboot - stoneyridge - fix sata.c 62200375 Kahlee: coreboot - clean up stoneyridge smbus files 62200225 Kahlee: coreboot - cleanup magic southbridge registers 62199625 Kahlee: coreboot soc cleanup - remove unused and non NULL function pointers and empty functions 62199225
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Marc Jones (Code Review)