Change in coreboot[master]: soc/intel/common: Add APIs to check CSE's write protection info

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/62986 )

Change subject: soc/intel/common: Add APIs to check CSE's write protection info
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soc/intel/common: Add APIs to check CSE's write protection info

The patch add APIs to check CSE Region's write protection information.
Also, adds helper functions to get the SPI controller's MMIO address
to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read
protection details.

During the coreboot image build, write protection is enabled for CSE RO.
It is enabled through a GPRD register which is part of Descriptor
Region.

TEST=Verify write protection information of CSE Region

Signed-off-by: Sridhar Siricilla 
Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b
---
M src/soc/intel/common/block/include/intelblocks/spi.h
M src/soc/intel/common/block/spi/spi.c
2 files changed, 95 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/62986/2