[S] Change in coreboot[main]: soc/intel/mtl: Add Intel RMT+ support

[Gaggery Tsai (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Jérémy Compostella, Kane Chen, Karthik Ramasubramanian, Krishna P Bhat D, Pratikkumar V Prajapati, Ravishankar Sarawadi, Ronak Kanabar, Subrata Banik, Tarun, Tarun Tuli, V Sowmya, Wonkyu Kim.

Hello Anil Kumar K, Bora Guvendik, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Jérémy Compostella, Kane Chen, Kapil Porwal, Krishna P Bhat D, Pratikkumar V Prajapati, Ravishankar Sarawadi, Ronak Kanabar, Subrata Banik, Tarun, Tarun Tuli, V Sowmya, Wonkyu Kim, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/77257?usp=email

to look at the new patch set (#18).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/mtl: Add Intel RMT+ support
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soc/intel/mtl: Add Intel RMT+ support

This patch adds Intel RMT+ (Rank Margin Test Plus) support on MTL.

BUG=b:293441360
TEST=1. Build an image with SOC_INTEL_RMT_PLUS_IN_DEV_MODE enabled
     2. Deploy the image to a Rex device
     3. Ensure /sys/firmware/acpi/tables/BDAT is exported from kernel.

Change-Id: Ieeaa8faf059bed90fca5029d4274db431b4eebea
Signed-off-by: Gaggery Tsai 
---
M src/soc/intel/meteorlake/meminit.c
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/77257/18