[S] Change in coreboot[main]: cpu/x86/64bit: Allow to map more of the address space

[Patrick Rudolph (Code Review)]

Attention is currently required from: Jérémy Compostella.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86580?usp=email )

Change subject: cpu/x86/64bit: Allow to map more of the address space
......................................................................

cpu/x86/64bit: Allow to map more of the address space

On AMD platforms the SPI flash can be accessed using the ROM3
mapping in upper MMIO space. To reach the MMIO window the default
page tables must be extended to cover the address by default.

Add support for a SoC specific default address space being used on
x86_64, where the default of 4GiB/512GiB remains.
The size can be specified by the Kconfig CPU_PT_ROM_MAP_GB option.

Used in the following patch to use ROM3 mapping on AMD platforms.

TEST: Access ROM3 bar at 0xfd00000000 on amd/birman+

Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462
Signed-off-by: Patrick Rudolph 
---
M src/cpu/x86/64bit/pt.S
M src/cpu/x86/64bit/pt1G.S
M src/cpu/x86/Kconfig
3 files changed, 19 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/86580/1

diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S
index 4b2f3c8..55d3ed0 100644
--- a/src/cpu/x86/64bit/pt.S
+++ b/src/cpu/x86/64bit/pt.S
@@ -20,16 +20,18 @@
 .global PM4LE
 .align 4096
 PM4LE:
-.quad _GEN_DIR(PDPT)
+.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
+.quad _GEN_DIR(PDPT + 4096 * ((. - PM4LE) >> 3))
+.endr

.align 4096
 PDT: /* identity map 2MiB pages */
-.rept 2048
+.rept 512 * CONFIG_CPU_PT_ROM_MAP_GB
 .quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3))
 .endr

.align 4096
 PDPT: /* Point to PDT */
-.rept 4
+.rept CONFIG_CPU_PT_ROM_MAP_GB
 .quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3))
 .endr
diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S
index 3502964..3a0e4b5 100644
--- a/src/cpu/x86/64bit/pt1G.S
+++ b/src/cpu/x86/64bit/pt1G.S
@@ -20,10 +20,12 @@
 .global PM4LE
 .align 4096
 PM4LE:
-.quad _GEN_DIR(PDPT)
+.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
+.quad _GEN_DIR(PDPT + 4096 * ((. - PM4LE) >> 3))
+.endr

.align 4096
-PDPT: /* identity map 1GiB pages * 512 */
-.rept 512
+PDPT: /* identity map 1GiB pages * CONFIG_CPU_PT_ROM_MAP_GB */
+.rept CONFIG_CPU_PT_ROM_MAP_GB
 .quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3))
 .endr
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 828c0f9..ae94f62 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -159,6 +159,15 @@
      Select this option from boards/SoCs that do not support the Page1GB
      CPUID feature (CPUID.80000001H:EDX.bit26).

+config CPU_PT_ROM_MAP_GB
+	int
+	default 4 if NEED_SMALL_2MB_PAGE_TABLES
+	default 512 if !NEED_SMALL_2MB_PAGE_TABLES
+	help
+	  GiB of the lower address space to identity map when using x86_64
+	  page tables in ROM. Higher values require more space in SPI flash.
+	  SoC can overwrite the value if necessary.
+
 config SMM_ASEG
    bool
    default n