Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50288 )
Change subject: [UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA ......................................................................
[UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
This still needs to be verified on real hardware.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527 --- M src/soc/amd/picasso/include/soc/iomap.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/50288/1
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 4031fa0..80c3f46 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -78,7 +78,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x13) +#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x10) /* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */ #define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */